What Advances Synopsys' Executives Expect In EDA Technology

Recently I had an exchange with a few Synopsys' executives about what they foresee for 2014. What follows is their input.


Michael Sanie, Senior Director, Verification Marketing, Synopsys

SoCs are growing in unprecedented complexity, advanced low power techniques and increasing amount of embedded software. In addition, time-to-market and competitive pressures are further compounding verification complexity. The current trends in complexity have begun to show signs that they will soon outpace what’s currently available in verification technology and methodology. In 2014, the industry will begin its journey into new levels of verification integration and productivity. Shaped on what has already been recently introduced, such as SystemVerilog, UVM, coverage planning and management, next-generation verification IP, advanced debug, and native low power simulation, higher levels of productivity will need to be enabled as simulation, acceleration, emulation, formal and debug technologies will begin to integrate in innovative approaches. As we head towards these next generations of technology and their integration, the SoC teams will see higher levels of productivity making verification schedules much more manageable and predictable.

Mixed-Signal Verification

Steve Smith, Senior Director of Marketing, Mixed-Signal Verification, Synopsys

The consumer electronics industry is driving for ever smarter mobile devices, along with their related requirements for faster performance, lower energy consumption and smaller form factor. This is accelerating convergence of disparate functional blocks within electronic systems, resulting in a growth of mixed-signal design starts. Many of our customers are packing their designs with multicore processors and other high-performance digital circuits, but there is increasingly a lot of analog and mixed-signal circuits integrated in there too -- for audio amplifiers, wireless modems, data communication interfaces and so on. Integrating all of these together in a single SoC or a multi-die package pushes the complexity of not only the chip design but also the verification process.

To ensure adequate functional coverage of complex digital and analog interfaces, and safety and reliability requirements, verification teams must now run large numbers of regression tests throughout the design and signoff phases. In order to achieve the best functional accuracy and debugging details, SPICE netlists of analog and mixed-signal blocks must be co-simulated with digital models and testbench. As a result, one of the biggest challenges facing verification teams is the relatively long time it can take to run full mixed-signal simulations. In the digital domain there have been a number of innovations introduced to boost verification throughput and quality in recent years, including SystemVerilog testbench, assertions and verification IP; low-power verification and advanced debugging and visualization. During 2014 and beyond, we will see increased use of regression testing for analog/mixed-signal designs where these, and other, metric-driven verification techniques will be broadly deployed.

IP Trends

John Koeter, Vice President of Marketing, Solutions Group, Synopsys

- Shift to finFET technologies for advanced chipsets in enterprise and high-end consumer markets, interface IP will need to meet power, performance and area targets; mixed-signal blocks will need to follow the digital scaling laws, digital blocks will include novel power gating techniques
- 28-nm will remain a dominant node for chipsets going into cost effect smart-phone markets
- Early adopters for USB 3.1, LPDDR4, DDR4-3200 and PCIe 4 towards the end of 2014
- HDMI 2.0 will drive 4k DTV adoption
- UFS 2.0 will become the preferred storage protocol for high-performance application processors
- Optical interconnect not likely happen in 2014 as integrated drivers/transceivers not possible in CMOS
- Battle on the display connectivity front between eDP, DSI and LVDS, sensor companies
- Trend towards optimized memories and libraries for specific processors
- Integrated test and diagnostic wrappers a must for all IP in the deep sub-micron nodes