Every January, or February if you are EDAC, leaders of our industry forecast what will be important and how the financial picture of EDA will be in the coming year. This year has not been different. I have chosen just three such forecasts. I want to highlight both non-traditional and traditional sources. Progress comes from looking at things from different points of view, and traditional financial analysis is much better than wild-eyed wishing. I could not resist, of course, from providing my own observations.

Kilopass

Kilopass is a company that offers embedded non-volatile memory intellectual property. It has just published its first issue of its newsletter, MemoryPill. In it Charlie Cheng, President and CEO, looks at 2012. He expects that power consumption consideration will outweigh die cost in the choice of process to be used for manufacturing. he also expects Japanese electronic companies to begin a strong resurgence in SoC design for mobile phones and cloud gears. And finally Mr. Cheng sees 2012 as the year that 3D packaging will finally become a reality with the introduction of reliable TSV vias connecting memories with the rest of the system.

Atrenta

In a blog (http://www.eetimes.com/electronics-blogs/other/4235158/Predictions--The-...) with the somewhat confusing byline of Brian Bailey, Mike Gianfagna, VP of Marketing at Atrenta revisits an idea first explored a few years ago by Peggy Aycinena. He predicts that TSMC will acquire Synopsys and that, as a result, GlobalFoundries will buy Cadence. Mike is exceptional in following the logic conclusions of events and certainly does not disappoint here. Mentor Graphics will shed some units, Calibre will go to a third foundry to be named later, and EDA will focus on system level design leaving preparation and production of chips to the foundries.

Griffin Securities

I must confess I did not even know of Griffin Securities existence until Jay Vleeschhouwer joined them. Jay is a leading analyst of our industry and seldom wrong in his predictions. It pays to find a way to receive his work if you happen to have any financial responsibility in your company. On january 23rd jay published a very detailed analysis of the EDA industry focusing in particular on the big three: Cadence, Mentor, and Synopsys. The document contains a lot of information that is outside the focus of this piece, but his predictions for 2012 are that the industry will see some growth, in the single digit range, not the 11-12% of 2011. The 2011 results were fueled by a significant increase in bookings, around 14% says Jay, with Synopsys accounting for about half of the growth.

My View

I believe that 2012 will be a year of settling on by now proven processes while the foundries work to make the 20 nm process reliable and practical. This does not mean that there will not be any commercial product produced with this node. It means, though, that the only very deep-pocketed companies will be able to afford resting the development flow required for this process. The most important reason for Mike Gianfagna's prediction is the extremely close working relationship required among developer, EDA vendor, and foundry to succeed at the 20 nm node. A relationship that becomes even more intimate at 14 nm. But does this mean that it will be necessary for the foundry to own an EDA company? I do not think so. The foundry can have its cake and eat it too. The leading EDA companies with proven complete design flows (Cadence and Synopsys) will have to be subservient to the foundries in order to survive. The foundries, on the other hand, can use the EDA vendors with success without having to deal with the complex and risky financial issues that an acquisition would require. Managing an EDA company is not easy, and if for example TSMC should acquire Synopsys, the company will now become a total overhead charge to be factored in the cost of doing business. As things are now, Synopsys (and Cadence and the Calibre portion of Mentor) have no choice but to invest in collaborating with the foundry to insure that their products can be sold.

I do agree, though that EDA vendors need to focus on system level issues in order to survive, especially if they do not happen to be Cadence or Synopsys. The extreme integration required by targeting 20 nm or below processes from synthesis on, will leave little if any space to grow for small companies. In addition some of the problems seen during this flow can be avoided or minimized through better system level design and verification. Furthermore, software integration is more important than elegant hardware design. Thus explorations of hardware/software integration and interaction increase in importance and thus command higher prices. This, in turn,, makes the system level market more attractive.

In the financial space Cadence has been for a few years the second largest EDA company in terms of revenue. One of the nuggets I found in Jay's report is that Mentor is second in earning per share and is rapidly gaining ground on Cadence in terms of corporate financial health. This year might be the year that Mentor surpasses Cadence in revenue, something Mentor, on the strength of some analytical rule employed by Gary Smith, already claims to have happened. The result is that in 2012 I expect to see an end to the speculations of Cadence acquiring Mentor and see the direction reversed with rumors that Mentor will purchase Cadence in order to strengthen its PCB, analog, and Calibre businesses.

The consolidation of manufacturing around the 65 to 32 process nodes will in fact give more emphasis to power consumption over die cost. There are two principal reasons for this. The difference in product development cost between 65 nm 45 nm and 32 nm will shrink considerably while consumer products will differentiate even more on the amount of battery life they offer.

I also think that Charlie Cheng is correct when it comes to packaging. The significant increase in software utilization increases the role of memories in the system. Not only the amount of memory, but especially the power they consume. A 3D packaging solution lowers power consumption. The difficulties of laying out the chip in 3D will be significantly diminishes with the introduction of a standard via geometry and placement. This is something that is needed and is not that difficult form an engineering point of view. The political hurdles will be overcome by the practical imperative of getting it done or loose income.

The year of the Dragon will indeed be an interesting time for the EDA industry.