As I have already written more than once, the 20 nm process is introducing a new reality in IC design and manufacturing. This is just a preview of how much harder things are going to be at 14 nm. Third party confirmation did not make me wait long. A press release from Synopsys contained the following statements.

From Synopsys Communication

At 20nm, as with prior process-node transitions, the challenges of managing power, performance, capacity and variability become progressively complicated. But, 20nm also introduces a clear, new challenge -- double patterning technology (DPT). This places an unprecedented burden on place and route tools to efficiently generate a layout which not only meets the traditional metrics mentioned above, but also can be decomposed into dual alternating patterns without undue impact on performance or device area.

Typical solutions for DPT either force full complexity of DPT in the place and route tool, incurring potentially large runtime and die-size overhead, or rely on an implement-then-verify approach to verify DPT correctness with a physical verification tool, risking multiple schedule-destroying iterations. Synopsys' IC Compiler-Advanced Geometry is built on award-winning Zroute and IC Validator In-Design physical verification technologies to deliver a noticeably superior DPT solution that minimizes die size and timing overhead while enabling the fastest path to design closure. Synopsys' approach to DPT keeps place and route performance efficient and avoids late-stage surprises, speeding the final tapeout. IC Compiler's DPT enhanced placement engine and Zroute routing technology work in tandem to efficiently generate a DPT-aware layout that can be verified and repaired for residual DPT violations using In-Design physical verification with IC Validator. GLOBALFOUNDRIES is actively partnering with Synopsys to offer this flow concurrently with the commercial release of its 20-nm technology.

Synopsys, Inc. announced that IC Compiler-Advanced Geometry (AG) drove silicon success for GLOBALFOUNDRIES' first major 20-nanometer (nm) chip. Recently announced, IC Compiler-AG is the 20-nm edition of IC Compiler. The tapeout of this large design containing a dual-core processor represents a major milestone in the collaboration between Synopsys and GLOBALFOUNDRIES to develop 20-nm rules and a comprehensive double patterning technology (DPT)-aware implementation solution.

Back to my View

Of course, this and one previous announcement only talk about tapeout and not about actual yield, which is really what counts. I do not expect a large flow of new designs targeting the 20 nm process any time soon, that is in 2012. Undoubtedly there are a few companies that need to use this process as soon as possible, but few, in today's economy, have the money to gamble on missing a market window just to increase design integration or experiment with ways to decrease power consumption by using smaller geometries.

It is interesting that the latest post by John Cooley at http://www.deepchip.com/items/0496-05.html contains the following quote from Rajeev Madhavan:
"I believe that within five years only two EDA companies will survive.
We will therefore be one of these two big companies, or we will have
been bought by one of them."

- Rajeev Madhavan, Magma CEO at the Silicom Ventures LLC
summit in Israel on June 30th, 2008

I believe that the prediction was not at all based on the financial projection of the EDA industry, but to realization that semiconductor fabrication technology will get so complex that the entire design chain will have to be strictly coordinated among the designing company, its EDA partner and the chosen foundry. And foundries will have neither the time nor the resources to collaborate with more than two EDA suppliers at the same time.