A couple of recent press releases from both Cadence and Synopsys provided information that widens the usability of the 28 nm process to a larger segment of system companies. First Cadence announced success in using its DDR4 design IP in TSMC 28HP and 28HPM processes. Shortly after ward Synopsys wrote that its 28 nm DesignWare IP had been successfully used in more than 30 test chips for the 28 nm process.
On September 4 Cadence made public the news that its DDR4 SDRAM PHY and memory controller design intellectual property (IP) family had been proven in silicon on TSMC's 28HPM and 28HP process technologies. Cadence has received and characterized multiple versions of its DDR PHY and controller IP in 28nm silicon based on advanced drafts of the DDR4 standard. These units are available immediately.
The proposed DDR4 standard, anticipated to be released by JEDEC later this year, will offer users substantial performance benefits over DDR3. DRAM devices adopting the DDR4 standard are expected to have 50 percent higher operational frequency and double the memory capacity of DDR3 devices while reducing the power consumed in the DRAM by as much as 40 percent per bit transferred.
The Cadence PHY family includes a high-speed implementation of the DDR4 PHY that exceeds the data rates specified in the DDR-2400 draft, meeting the requirements of next-generation computing, networking, cloud infrastructure, and home entertainment devices, while offering interoperability with current DDR3 and DDR3L standards. Also proven in TSMC 28HPM silicon, is a low-power, all-digital mobile PHY implementation that exceeds the data rates called for in both the DDR-1600 and DDR-1866 DDR3 standards and the maximum data rate of the low-power LPDDR2 standard. As a result, SoC designers can now deploy fast, power-efficient memory technologies in next generation mobile designs with confidence.
On September 5, Synopsys announced the 100th design win of its DesignWare IP optimized for 28-nanometer (nm) processes for multiple leading foundries. The silicon-proven 28-nm portfolio consists of IP including PHYs for USB, PCI Express, SATA, HDMI, DDR, MIPI, as well as data converters, audio codecs, embedded memories and logic libraries, with tens of millions of units shipped.
Synopsys' 28-nm DesignWare IP has been thoroughly silicon-characterized across process, voltage and temperature (PVT) variations in both High-K Metal Gate and PolySiON technologies to ensure design robustness. By having taped out more than 30 test chips in more than ten different 28-nm process nodes, with products shipping in volume production, Synopsys provides designers with high-quality DesignWare IP solutions that can be quickly integrated into a range of system-on-chip (SoC) applications such as mobile applications processors, multimedia graphics networking and storage with less risk and effort.
Advanced process geometries present additional design challenges in SoCs and IP development. At the 28-nm process node, design rules, leakage power and I/O voltages are substantially different than those in 40- and 65-nm processes. To address 28-nm design requirements, Synopsys modified key design aspects of its IP, while adhering to industry protocol specifications and ensuring reliable operation. For example, to meet manufacturing requirements, Synopsys implemented more than twice the number of restrictive design rule checks for its 28-nm IP compared to the 65-nm process and eight times the number of PVT corners for thorough validation. Furthermore, Synopsys employed advanced low-power design methodologies to address low leakage requirements.
Synopsys developed its 28-nm DesignWare embedded memories using statistical design methodologies to address design variability challenges and incorporated multiple power management features including source biasing and dual voltage rails to deliver up to 70 percent leakage power reduction. DesignWare Logic Libraries incorporate multiple threshold voltage and long channel devices to reduce SoC leakage power. In addition, the Logic Libraries are characterized across a wide range of corners, enabling designers to reduce dynamic power through the use of Dynamic Voltage and Frequency Scaling (DVFS) techniques. These features and design techniques enable designers to successfully integrate 28-nm DesignWare IP into their advanced SoC designs to improve performance, power and area results.
The DesignWare PHY IP for USB 3.0, USB 2.0, USB HSIC, DDR3/2, LPDDR3/2, PCIe 2.0, SATA I/II/III, HDMI 1.4, MIPI M-PHY, MIPI D-PHY, as well as embedded memories, logic libraries and data converters (analog-to-digital converters and digital-to-analog converters) for select 28-nm processes are available now.
The 28-nm DesignWare audio codecs are scheduled to be available to early adopters in Q4 of 2012.