NOTICE: The DVCon website was updated after the publication of this article. The Tuesday afternoon panel is now properly displayed to be one hour long, and Exhibits hours are also displayed on the right.
This year's edition of DVCon will start on Monday February 27. DVCon is the premier conference covering issues of functional design and verification dealing with subjects as varied as technology, techniques, standards, and methods. The conference is sponsored by Accellera Systems Initiative, the leading industry consortium that sponsors the development and support of standards for electronic design and verification.

Although the conference lists three media sponsors on its home page, one can only find a mention of the conference on the home page of Chip Design magazine, while there is no mention of the conference by either EDACafe or the RTC Group on their home pages. One of the problems, I fear, is a disconnect between Accellera and the DVCon management organization in spite of Accellera being represented on the Steering Committee by two members. Having two separate PR professionals, one for Accellera and one for DVCon is not the best possible solution to promote the event.

The Ten Thousand Meters View

Karen Bartleson of Synopsys is this year's General Chair. Karen, who has just been elected President of the IEEE Standards Association, has chosen to preserve the overall structure of the conference, wisely deciding not to change what is not broken. Both Monday and Thursday offer tutorial opportunities, while Tuesday and Wednesday are filled with technical program sessions, a keynote by Aart de Geus, and panels.

DVCon, contrary to DAC and DesignCon, has always chosen to include but minimize the commercial aspect of our industry. This is the case this year as well. Although attendees will be able to browse through exhibitors' booths, the hours in which the exhibits are open never conflict with the technical program. In fact the times the exhibits are open are not even advertised on the DVCon web page.

The venue also has remained the same. The DoubleTree Hotel by the San Jose airport is once more hosting the conference. For out of town attendees this is quite convenient because they can avoid renting a car and paying for parking which at the DoubleTree can be expensive.

Dr. Ambar Sarkar from Paradigm Works is the Program Chair. Aided by his Vice Chair Shankar Hemmady of Synopsys and thirty among the technology leaders of design and verification disciplines Ambar has developed a very interesting and compelling program.

My latest count shows 33 exhibitors, which include six first time exhibitors. The emphasis is on content, not booth showmanship. Most booth are the same size, with the obvious exception of the big three who need more space due to a larger inventory of products. There is no room for giveaways collectors here: this exhibit floor is for serious attendees only.

The Low Altitude Pass

So far over 750 attendees have registered and will benefit from a well thought out program. The emphasis, not surprisingly is on SystemVerilog and SystemC.

Monday

Monday morning the North America SystemC Users Group will hold its 17th meeting. This has become a tradition with DVCon and the merger of Accellera and OSCI has now cemented the relationship. Those interested in UVM, the Unified Verification Methodology can instead attend the first part of a tutorial organized by the three most visible Accellera representatives from the big 3: Dennis Brophy from Mentor, Stan Krolikoski from Cadence and Yatin Trivedi from Synopsys. The three companies worked together to develop the methodology and none of them is willing to relinquish the spotlight.

In the afternoon there is the opportunity to attend an introductory tutorial about the IEEE 1666-2011 standard, the new SystemC standard, or continue to learn about UVM. There are ten speakers for both parts of the UVM tutorial representing not only Cadence, Mentor, and Synopsys, but also both users and smaller EDA vendors.

A ninety minutes tutorial on the Accellera's Unified Coverage Interoperability Standard takes place on Monday afternoon as well and it is followed by a tutorial covering the verification and automation improvement by using IP_XACT.

A luncheon sponsored by the newly named Accellera System Initiative hopes to engender a discussion on the topic "What will success for the Accellera Systems Initiative look like?". Hopefully this is just a way to get feedback from the tutorial attendees, since the creators of the organization must have had some ideas of the focus, mission, and goals before the merger. First we build it and then we figure out how to use it has never been a good architectural approach, especially in electronics.

Tuesday

Tuesday morning, from 9 to 12:30 six sessions cover the spectrum of design and verification topics. A session on low power techniques discusses IP reuse, the use of UPF, the use of equivalence checking techniques, and the Power State Table. Speakers are mostly from the Big 3 with Sorin Dobre of Qualcomm the sole user representative.

Session 2 covers the use of UVM, and offers speakers from both user companies, training companies, and Cadence.

The other session in this time slot is titled "SystemC and Beyond" but reading the topics being covered it looks like the "beyond" is left to come. Speakers from user companies make up almost all of the presenters with only one speaker from an EDA vendor: Steve Anderson from Forte Design Ssytems.

During the coffee break attendees can visit the poster Session to network with students and designers eager to share their ideas.

Sessions 4 through 6 take place from 11:00 to 12:30. Session 4 called Verification Benchmarking and Efficiency deals with the SsytemVerilog environment and has a good mix of speakers. The third part of the session addresses plans for the next version of SystemVerilog.

If you are interested in formal techniques session 5 is for you. Speakers from both Jasper Design Automation and Real Intent join a strong field of users in covering this topic.

Session 6 addresses a very important topic: that of Mixed Signal Verification. UVM, OVM, and TLM techniques are covered by speakers from both users as well as Cadence and Mentor.

After such demanding sessions it will be nice to have lunch while earning a degree in Low Power Arts and Sciences. At least this is the promise from Cadence. May be the luncheon is an experiment by the company to penetrate a new market: higher education. After all there is money in it!

I must confess that I am quite puzzled about the afternoon program. It offers a three hours panel on the topic of the Resurgence of Chip Design. I really disagree with the description in the program. "Building your own ASIC is often the only way to reach the desired power, performance, and cost goals" only applies to a very small, and getting smaller, segment of electronics companies. I do agree that CPU's are not the only IC's that must be developed. GPU's, Network controllers, wireless communication processors are examples of ASIC that will continue to be developed, but traditional ASIC chips are now so expensive to make most of them impractical.

The good news is that if you attend you get to hear Ted Vucurevich who has re-emerged after leaving Cadence,. But you will also have to listen to Gary Smith and Jim Hogan both of whom have been overused in the past 18 months as panelists.
But look ahead: the Exhibitors Reception will give you a way to end the day on a high note.

Wednesday

Wednesday program is just as busy as Tuesday's but it starts earlier, so people need to be ready to learn at 8:00 in the morning. Most professionals in the Valley are just getting up at that time of the day. The first three sessions in the morning are dedicated to verification so getting up is a must.

Session 7 offers verification and debugging tips mostly from actual users, although both Cadence and Mentor staff contribute to it. In fact the second part on TLM is totally presented by Cadence. Session 8 looks at ways to get to coverage closure. Once again Cadence and Mentor mix with actual users in providing tips to measure coverage. Session 9 cover UVM topics and benefits mostly from users' experience. Only one paper is authored by an EDA company: Mentor.

Another poster Session and another coffee break follow, after which the attendees should be ready for another session.

Session 10 covers more UVM material but this time it is Synopsys to dominate the program. Mentor, the most ubiquitous of the Big 3 also has a paper purporting to play marriage counselor. Paradigm Works fills the bill for this session. Session 11 presents verification case studies. Springsoft joins Mentor and Synopsys as presenters, although there is significant input from real users that make this session very interesting. Session 12, Verilog tips and techniques, concludes the list of technical sessions. Once again you will find contributions from Mentor and Synopsys together with input from Intel, Cisco Systems, and Dialog Semiconductor.

Lunch is sponsored by Synopsys that wants everyone to know that industry leaders verify with Synopsys. There is no free lunch even when money does not exchange hands.

I always find any talk by Aart de Geus a must event. The fact that Karen Bartleson is the general chair does not explain the reason Aart was invited to give the keynote speech. The unpublicized algorithm used to determine who will be the keynote speaker is in fact quite simple. The Big 3 take turns: and this year it was Synopsys turn.
Thinking back to the Tuesday luncheon one worth while suggestion would be to abandon the algorithm and let someone else have the floor. With all due respect, I believe that the Big 3 do not hold a monopoly on interesting ideas and observations. Making the most money should be satisfaction enough.

By I digress. Aart topic is actually timely and extremely important because it deals with a fundamental change in product development methods. The title is "Systemic Collaboration: Principles for Success in IC Design". Any designer, manager, and marketing professional must understand the topic and practice it if they are targeting any process below 45nm. But take note: these methods are required at 22nm and beyond. I wish this speech would take place before the Tuesday afternoon panel. I am sure the panelists' remarks would be quite different.

The final panel of the day deals with hardware assisted verification and asks the question: is it better to build or buy your hardware prototype? Having managed a few hardware development projects in my time I already know the answer, but you might find it instructive. You might want to listen since another exhibitor reception fallows the panel. And besides, although the program does not says it, at the end of this panel the technical committee will announce the best paper award. Contrary to most conferences, DVCon actually gives money to the winner.

Thursday

Another day dedicated to tutorials. By now you must have understood that DVCon is a serious conference that provides opportunities to learn and stimulates attendees to think and contribute.
Cadence is sponsoring Tutorial 5 that will cover the use of "apps" to take formal analysis mainstream. I think of it as IP for formal analysis. We will see if the "apps" will be free, or not. Tutorial 6 is sponsored by Mentor Graphics and deals with the design and verification of platform based, multi-core SoCs. The tutorial is three and a half hours long giving plenty of opportunity to at least present the complexity of such a task.

Jasper Design Automation will sponsor both the luncheon and Tutorial 7. During lunch the topic will be Formal Verification from Users Perspectives while the tutorial session covers techniques to leverage formal techniques throughout the entire design cycle. Tutorial 8 sponsored by Synopsys addresses Verification IP and how it can be used to improve productivity. Synopsys has entered the market for Verification IP with its usual enthusiasm so it will be interesting to hear what they have to say.

My advice: take Friday off and let all of this material soak in: I bet it will be worth while.