The first paragraph of the official release from Apache promises new help for designers. Power consumption is not just a problem for portable devices, but, translated in heat, is also a major issue with electronics that remain plugged to a socket. Therefore one cannot but rejoice from the announcement. Or can we? Based on the contents of the press release, many doubts remain starting with the title that implies a new model of not just power distribution but also a dynamic impact of power consumption on the circuit behavior.

Although a very attentive reading of the release limits the product of the new tool to be an optimized power delivery network, the contents aim to promise an optimum circuit behavior as far as power consumption and derivative effects, like heat and noise, are concerned.

It is of course the job of Marketing and Public Relations to find all possible patches of blue sky and make all clouds vanish from the reader's horizon. And thus, after reading the first paragraph of the official release, all engineering managers could be expected to pickup the phone and beg the Apache sales rep for at least one license, no matter the cost. Actually there are a few details missing in the wording. Some of them you can discover later on in the piece, and some that are just simply oversimplified. How power is delivered is of course important, but how it is consumed is critical.

The power consumption of an electronic circuit derives from the static and dynamic characteristics of its components, as well as the characteristics of the fabrication process chosen by the foundry. What components are used in the design contribute to its static profile. No matter how creative engineers get, no one can fool Mother Nature. Unfortunately after the introduction of HDL tools a majority of universities, especially American institutions, have focused on graduating logic designers, not electrical engineers with the required knowledge of physics. The result has been an emphasis on functional design that shifts the responsibility of physical integrity to the foundry or, at best, to the place and route team.

We all know that the approach is now broken, since analog effects of any circuit are directly impacting how logic is designed. Thus, Apache, a company that has dedicated all of its existence to solving power consumption problems, has naturally focused its attention to RTL design.

The Static Problem

The static limitation inherent in the description of the tool in the press release is the non-stated assumption of how a RTL description will be synthesized. Apache does not control any synthesis tool, either logic of physical. And these tools have become quite sophisticated in making implementation tradeoffs that are based on global, proximity, and local characteristics. The problem is that even small changes in a predicted circuit topology can have significant impacts in power consumption due to other second order physical "events". The other problem, of course, is the lack of a complete set of power consumption information from the foundry at the RTL level. There still exist a wall separating logic and physical implementations when it comes to the material characteristics of the implementation media (one can no longer just speak of silicon). So RPM does the best job it can with the information it has, but engineers must be very aware that it is the best guess, not a certainty as the press release states when it says that (bold added by me) "it accurately predicts integrated circuit (IC) power behavior".

The Dynamic Problem

Power consumption is not just a matter of the topology of a circuit, but also of how the circuit is utilized. Simulating how a circuit functions, both as an aid to logic design and as a verification of proper implementation, has been the most expensive part of product development for quite some time. One of the key issues of simulation is that one cannot make a definitive statement at any time that all possible states of the circuit have been simulated, with the obvious exception of very small circuits.

No one could argue that the dynamic functioning of an electronic circuit depends on its operation. Yet, when it comes to analyzing the dynamic power distribution requirements of a circuit, Apache's RPM relies totally on a subset of the available simulation vectors. The press release states that (bold added by me) "Fast Frame-Selector technology performs power analysis on RTL simulation vectors and selects a set of the most power-critical cycles to use throughout the design flow, from early design planning to final chip sign-off. It can accurately identify a few cycles representing the transient and peak power characteristics from millions of vectors within hours, improving productivity and ensuring power sign-off integrity."

The Fabrication Process

The one area where the press release is legally correct but practically misleading deals with the process technology supported by the RPM tool. in a couple of places it states that the tool is effective with designs targeted at 28 nm or below. The opening paragraph states that the tool (bold added by me) "to ensure chip power integrity sign-off for sub-28nm ICs." And toward the end you can read that (bold added by me) "It helps bridge the gap from front-end RTL design to physical power sign-off, with more predictable accuracy, increased operating performance, and greater reliability for 28nm and below designs."

From a legal point of view Apache is correct: the tool is very likely capable to produce the same quality of results at both 28 and 22 nm. So it is a tool that can be used to analyze circuits targeting a process below 28 nm. The problem for engineers, of course, is that there exist processes below 22 nm, with 20 nm already in the early stages of commercial implementations.

It is certainly not a guarantee that the power profile of a tri-dimensional transistor can be derived from that of a two dimensional one. Thus assuming that RPM will work below 22 nm is a leap of faith no engineers should be asked to make. The close cooperation publicly described in the very few published reports among EDA tool vendors (none including Apache), product designers, and foundries, shows how demanding it is to translate functional characteristics into a semiconductor device that can be manufactured. I have yet to read the results of tests of a manufactured product, and I do not expect to ever see such data from an IDM like Intel.

I am puzzled by the omission of the 45 nm process from the press release. It is clear that in the next two years at least, the majority of new products will target process technologies that span the 45 to 22 nm technologies. One can read the press release in various manners. One is that the power distribution and consumption at 45 nm does not present such critical problem, another is that RPM is too expensive to be used at 45 nm, and yet a third one is that the knowledge required from the foundry is not available in the 45 nm libraries.