Designers working on subsystems and systems using information for LED, semiconductor, and package components use complex thermal analysis software to help accelerate the design of their products but the analysis, typically based on vendor datasheets, often provides insufficient results. Clear, accessible, and reliable data relating to thermal characteristics upstream and downstream is critical. Methods to achieve this have traditionally been awkward, manual and therefore error-prone.
SpringSoft, Inc. has focused its attention of a portion of IC development that is generally performed using traditional place and route tools that have long execution time. Chip finishing very often requires local modifications to the layout, yet, using the tool required for a full place and route job means that much unnecessary work is performed. This leads to a waste of time since designers need to wait many hours, often up to half a day, to see the results.
Laker Blitz is a chip-level layout editor that is specifically optimized for speed and user productivity during the chip finishing stage of the IC/SoC design process. It loads and exports GDSII data files 5 to 20 times faster than conventional layout tools and offers more robust layout editing capabilities than most high-capacity layout viewers.
Laker Blitz targets a variety of chip finishing applications, including IP merging, SoC assembly, and chip-level DRC reviews, that are routinely performed by semiconductor manufacturers, foundries and fabless design companies.
Magma Design Automation announced the availability of a new release of the Titan Analog/Mixed-Signal (Titan AMS) Design Platform. With patent-pending analog design technology, Titan provides an innovative FlexCell-to-GDSII analog/mixed-signal (AMS) flow that organically integrates both electrical design and physical design into one unified design methodology. More than 30 customers, including the majority of the top 20 semiconductor companies in the world have adopted Titan AMS, according to Magma.
As I said a number of times, advanced process technology demands a close cooperation among all parties necessary to successfully transform a product idea into a profitable product. Thus at the tail end of the development process companies that offer mask making equipment and EDA vendors that provide the tools for producing the required patterns must work together to find an efficient compromise that lowers costs.
Mentor Graphics has made two announcements recently that focus on collaborations with industry partners for backend manufacturability tools. The first one with TSMC that addresses metal fill, and the second with NuFlare on mask generation.
Volume diagnostics are essential for efficiently determining the causes of silicon failures that cut into IC profit margins and impact time-to-quality. Developing a design and ensuring its manufacturability is not enough to insure the product’s profitability. An acceptable yield level must be achieved quickly, or the profit margin will be seriously compromised.
At 28 nm and below, certain patterns that reduce semiconductor yield are difficult to describe in process rules and are typically addressed using time-consuming and costly lithography process simulations. The pattern matching approach offers a faster, cheaper and comparably accurate alternative. Magma Design Automation announced that the new pattern matching capability in the Quartz™ DRC physical verification product has been qualified to support DRC+, GLOBALFOUNDRIES' silicon-validated, yield-critical pattern-based design for manufacturing (DFM) verification flow for all advanced process technologies, including 40 nanometer (nm), 28 nm and below.
TSMC has included the QCP™ extractor from Magma Design Corp. in TSMC’s quarterly EDA qualification report for 28-nanometer (nm) integrated circuits (ICs). This qualification gives designers additional confidence in using QCP to address the increasing complexity of ICs implemented in TSMC’s 28-nm processes.
Cadence seems to be implementing its "must have" list in alphabetical order. So after Altos it was Azuro's turn. Will a B company be next? Most people in our industry will agree that clock and power optimizations are important, but what I did not know was that Cadence was doing a poor job at it. And so the company found that some key customers were going to Azuro to purchase what they could not get from Cadence. The solution was obvious: purchase the annoying interloper before a real competitor would.