Home

Open Channel

Intel Capital Creates $300 Million Ultrabook Fund

Thu, 2011-08-11 07:57 — Gabe Moretti

Intel Capital today announced a $300 million Ultrabook™ Fund to help drive innovation in this new category of devices. As announced at Computex earlier this year, Ultrabook systems will marry the performance and capabilities of today’s laptops with tablet-like features. Ultrabook devices will deliver a highly responsive and secure experience in a thin, light and elegant design at mainstream prices.

Oasys Design Systems Enhances Chip Synthesis with Power Capabilities

Fri, 2011-02-25 09:59 — administrator

Oasys Design Systems today unveiled the latest version of its revolutionary Chip Synthesis™ platform with enhanced capabilities that include chip-level power analysis and the ability to re-synthesize a design from the register transfer level (RTL) with new power constraints.

Evatronix Facilitates Chip-to-chip USB Connectivity with Its USB HSIC PHY

Wed, 2011-02-16 16:52 — administrator

Evatronix SA, announced the introduction of a High Speed Inter-Chip (HSIC) compatible PHY IP for significant power and area savings in USB 2.0 chip-to-chip connections. Implementation of the HSIC technology enables setting up a direct connection on a PCB board between a USB Host chip and other on-board USB devices. The HSIC standard features reduced power consumption thanks to elimination of requirements to support long external USB cables while remaining USB protocol compliant and thus USB software compatible. The possibility for straightforward use of all the available USB software gives HSIC an advantage over other inter-chip connection standards, like I2C.

SynthWorks announces Methodology and Open-Source Packages for Constrained Random Tests in VHDL

Tue, 2011-02-08 07:59 — administrator

SynthWorks announced its VHDL based constrained random and coverage driven random testbench methodology. At the heart of this methodology are packages for randomization and functional coverage that SynthWorks' has released as an open source download.

Kilopass Announces Record Revenue in 2010

Mon, 2011-01-31 16:16 — administrator

Kilopass Technology Inc., a leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP), today announced record revenue in 2010, posting 100% year-over-year growth in its core business, coming off a strong 2009 that enjoyed significant custom IP development.

CEVA’s New DSP Core Delivers Audio Performance, Flexibility, and Codec Support

Thu, 2011-01-13 09:56 — administrator

CEVA, Inc. announced the latest addition to its CEVA-TeakLite-III DSP architecture. The CEVA-TL3211 is an advanced DSP targeting the growing needs of low cost smartphones and high-definition (HD) audio features within digital televisions (DTV), set-top-boxes (STB), and Blu-ray Disc players. The CEVA-TL3211 delivers the industry’s highest levels of performance, power efficiency, user flexibility, and smallest memory footprint to address the requirements of 2G/3G modems and advanced audio processing, including fully-certified HD audio codecs from Dolby and DTS. This new core has already been adopted by a Tier-1 semiconductor vendor.

S2C Released 7 New Pre-Engineered Prototype Ready™ Accessories

Mon, 2011-01-10 17:03 — Gabe Moretti

S2C Inc.has announced the addition of 7 new Prototype Ready accessories to its growing library of pre-engineered hardware and software components aimed at speeding the development of SoC prototypes. These modules work with S2C’s TAI LM family of rapid SoC prototyping tools.

Agilent Technologies Introduces Design and Test Solution for 3GPP LTE-Advanced

Thu, 2011-01-06 13:02 — administrator

Agilent Technologies Inc. announced the industry’s first commercially available 4G system design library for 3GPP Release 10 -- the W1918 LTE-Advanced library. The new system design library is available as an option to Agilent’s SystemVue 2011.03 release software. Wireless system architects and chipset makers working to provide the 4G network 1-Gbps peak download speed can now use Agilent’s W1918 LTE-Advanced library for earlier verification of physical layer (PHY) algorithms and system performance.

2011: The Year of U.S. High-Level Synthesis Deployment

Wed, 2010-12-15 15:20 — Anonymous

Brett Cline, Vice President of Marketing and Sales, Forte Design Systems

High-level synthesis has been in production use in Asia for nearly a decade. And, while you’ve been able to buy products from leading Japanese and Korean vendors at your local Best Buy for several years, U.S. companies haven’t widely deployed the technology … yet. That is all about to change.

2011: Chips Not Blocks

Wed, 2010-12-15 15:16 — Anonymous

Paul van Besouw, President and CEO, Oasys Design Systems

2011 is going to be the year that a lot of 28nm designs are going to be undertaken and the design methodology defined. This is going to stretch the current block-based approach beyond breaking point.