CoWare Inc. announced the availability of a new Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect, enabling early and efficient optimization of next-generation system-on-chip (SoC) architectures using ARM® AMBA®-based virtual platforms.
Synopsys, Inc. has released new advanced analog simulation and layout capabilities in its Galaxy Custom Designer implementation solution.
Accellera and The Spirit Consortium have decided to merge, and no shotgun was in sight. How cool is that? This event is very positive for both the EDA and the semiconductor industry.
Cadence has announced that further restructuring is required in order to achieve profitability in a reasonable amount of time. The measures are designed to further streamline operations and position the company for its next growth phase.
Synfora, Inc.announced PICO Extreme Power to reduce power consumption, which is a major consideration in designing mobile devices.
To prove that technological capability is still the key ingredient in a customer choice of tools, Magma has started a new marketing program: try it for free. Potential customers can try the Quartz DRC and Quartz LVS physical verification tools for free for sixty days to see for themselves whether or not the results justify the purchase of licenses.
Mentor Graphics Corporation has announced the availability of the next-generation PADS flow with the introduction of PADS 9.0.
Magma Design Automation Inc. reported revenue of $34.1 million for its fourth quarter and $147.0 million for its 2009 fiscal year, both ended May 3, 2009. In the fourth quarter Magma generated cash flow from operations of approximately $5.5 million.
Magma Design Automation Inc. has announced the release of Talus 1.1. The product utilizes the new Talus COre technology, which leverages Magma’s unified data model to perform timing optimization concurrently during routing, thus providing faster overall design closure with better performance and predictability.
Zuken is introducing a new bridging technology to the CADSTAR design suite - CADSTAR BoardModeler Lite. This technology provides an optimized environment for the verification of the PCB layout in its mechanical environment. BoardModeler Lite creates a bridge between the ECAD and MCAD world using the industrial formats which are in common use in the MCAD world, namely ACIS, STEP, and STL format.