Increasing amount of firmware in SoC devices requires bigger and faster memory subsystems. Synopsys announced the expansion of its DesignWare DDR interface IP portfolio to include support for next-generation SDRAMs based on the DDR4 standard. By supporting DDR4 as well as DDR3 and LPDDR2/3 in a single core, the DesignWare DDR solution enables designers to interface with either high-performance or low-power SDRAMs in the same system-on-chip (SoC), which is a key requirement of many SoCs such as applications processors for smartphones and tablets.
EVE has announced immediate availability of the e-zTest MIPI CSI-2 and e-zTest MIPI DSI validation platforms.
These two new wireless system-on-chip (SoC) validation platforms support the Mobile Industry Processor Interface (MIPI) Alliance wireless standards for Camera Serial Interface (CSI-2) and Display Serial Interface (DSI). They allow fast configuration of virtual cameras and virtual displays, along with an interface to a device under test (DUT) in the high-performance ZeBu SoC emulation system. The virtual test environment offers network accessibility of the design to any hardware or software engineer.
Last week I had the opportunity of speaking with Becky Oh, CEO of PNI Sensor Corporation. Those who follow this column know that in the last couple of years I have become interested in the MEMS industry. It all started during the GlobalPress 2011 event, when I listened to a few presentations from MEMS technology companies. This industry is very interesting on a number of dimensions: the semiconductor technology they use, the physics of the devices they produce, the amazing complexities of their micromachines, and the lack of integration tools from EDA companies.
Everyone loves a good underdog story. In EDA, that covers about 98% of the suppliers. There are lots of them. In an industry in which three companies with broad product lines control the vast majority of the revenue, about 200 other companies, with point tools principally, battle the giants head-to-head in their own narrow product space.
I received my Master Degree in Computer Sciences a little over forty years ago. The subject of my thesis was a computer based testing system for the manufacturing floor of the company I was working for. Another engineer who developed the hardware and myself developed a system to test incoming chips and completed PC boards in manufacturing. A minicomputer stored the tests and the results so that we could not only screen bad items, but also collect data about batches of incoming parts.
Last year I attended Zuken World (now renamed Zuken Innovation World) in San Antonio TX, but did not meet either of the Castro twins. Instead I attended the release of the CR-8000 PCB design environment and learned a lot about a company that at times seems a bit shy in its marketing approach in the US. Its style contrasts with the more aggressive approach of its competitors. I have often speculated that this is due to different cultures in Japan and in the US. Zuken, enjoys a significant place in the PCB market, competing with Mentor for leadership in the market. The CR-8000 is truly a system level design environment that approaches PCB architecture, design, and implementation in a holistic way.
The news that Samsung Venture Investment Corporation has invested $4 million in Carbon Design Systems is a clear indication that Carbon's products have achieved a critical place in the design flow at Samsung. Obviously Samsung cannot run the risk of seeing a small company as Carbon disappear, and can also leverage thje investment should an acquisition happen in the future.
Mentor Graphics Corporation has updated its Universal Verification Methodology Connect (UVM Connect) to bring the benefits of it to the Open Verification Methodology (OVM) community. UVM Connect has been extended to allow it to be compiled to run with the OVM. The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With UVM Connect 2.2, teams using OVM can connect with SystemC models and other environments as well.
A couple of recent press releases from both Cadence and Synopsys provided information that widens the usability of the 28 nm process to a larger segment of system companies. First Cadence announced success in using its DDR4 design IP in TSMC 28HP and 28HPM processes. Shortly after ward Synopsys wrote that its 28 nm DesignWare IP had been successfully used in more than 30 test chips for the 28 nm process.
Title: When to Retool the Front-End Design Flow?
By Rick Eram, Director of Sales and Field Operations at Real Intent