Virage Logic announced the availability of its new ARC 601 32-bit microprocessor core, the first ARC processor Virage Logic has brought to market since its acquisition of ARC International.

Taiwan Semiconductor Manufacturing Company, Ltd. unveiled modular BCD (Bipolar, CMOS DMOS) process technologies targeting high voltage integrated LED driver devices.

CEVA, Inc. and Gennum Corporation’s Snowbush IP Group announced that they have partnered to deliver a complete Serial Attached SCSI (SAS) 2.0 IP solution optimized for embedded storage applications. The integrated offering combines Snowbush silicon-proven 6.0Gbps PHY IP integrated with CEVA’s SAS 2.0 Controller IP, offering the industry’s most mature and feature rich SAS 2.0 IP solution.

The Open SystemC Initiative (OSCI), an independent, non-profit organization dedicated to supporting and advancing SystemC as an industry-standard language for electronic system-level (ESL) design, celebrates its 10th Anniversary this year, a decade marked by a series of major milestones for the group, including official IEEE (Institute of Electrical and Electronics Engineers) approval of the SystemC language as IEEE Std. 1666-2005, "Standard for SystemC," in December 2005, and the release of the OSCI transaction-level modeling standard, TLM-2.0, in June 2008, promoting the sharing and exchange of high-level models.

Aldec Corporation has released its latest Design Rule Checking application, ALINT 2009.10. The product includes “best-practice” design rules for fast design closure of safety critical DO-254/ED-80 Avionics designs. ALINT 2009.10 offers a set of VHDL or Verilog design rules optimized to detect HDL code, design and verification issues including: design recoding practices, design reviews and safe synthesis guidelines. The new DO-254 design rule plug-in provides guidance to help achieve DO-254/ED-80 compliance for FPGA designs that reside within a system.

Carbon Design Systems announced immediate availability of an array of implementation-accurate models of ARM intellectual property (IP) cores. The expanded portfolio of Carbonized ARM IP now includes the entire Cortex and ARM11 families of processors, along with ARM9 and ARM7 family of processors. In addition, it includes support for the ARM AMBA NIC301 Network Interconnect, as well as the most popular AMBA AXI, AHB and APB peripherals.

Maia EDA, based in Cambridge Great Britain, has announced the availability of the Maia functional verification tool. Maia uses a description of the expected behavior of a device to automatically create a complete self-checking reactive testbench. Maia is primarily targeted at hardware engineers who write and need to verify their own RTL code, but a key benefit of the tool is that it can be used by staff who have no knowledge of Verilog or VHDL (although at this time it only supports Verilog), and who have only minimal programming skills.

The IEEE Council on Electronic Design Automation (CEDA) today announced the formation of the Design Technology Committee. This newly formed group under CEDA will focus on the viewpoint of the major EDA users in identifying future needs of the system and semiconductor communities toward the EDA industry.

Agilent Technologies Inc. announced the release of its RFIC simulation, verification and analysis software -- GoldenGate version 4.4. This release offers enhanced performance, new key stability and yield analyses, and RF extensions to mixed-signal simulation. In addition, the new release brings performance and flexibility updates to its unique wireless standards-based virtual test bench capability. The new release, available this month, has a starting price of under $25,000.

Berkeley Design Automation, Inc. announced Analog FastSPICE RF (AFS RF. Available immediately, AFS RF analyzes nanometer-scale device noise impact for all types of pre-layout and post-layout circuits, ensuring early insight into its impact on performance, power, and area.