Continuing its tradition of promoting and recognizing printed circuit board (PCB) design excellence, Mentor Graphics Corporation announced winners of its PCB Technology Leadership Awards. Started in 1988, this program is the longest running competition of its kind in the electronic design automation (EDA) industry. It recognizes engineers and designers who use innovative methods and design tools to address today’s complex PCB systems design challenges and produce industry-leading products.

During the last few days, I have received a number of press releases from both Cadence and Synopsys dealing with their work with TSMC on the 20 nm process. It then makes sense for me to hear from Mentor Graphics as well. Their news, unlike their two direct competitors, did not specifically focus on 3D-IC technology, although a tweet from Dennis Brophy chirped about it, but instead deals with a broad range of tools.

Although both CEDA and EDAC have tried to put a positive spin to this change, this is another sign of the significant transformation of the EDA industry. Moving the Phil Kaufman award to Sunday evening at DAC is like taking two aspirins and calling the doctor in the morning.

Last week I wrote that TSMC had validated Synopsys' design flow on its 3D-IC process. Today I received a press release from Cadence stating fundamentally the same thing with regard to its design flow. It is clear that work on 20 nm processes is intensifying as a way to justify the significant investment required by system companies to use it.

May be you think the 3D-IC pace of development is too slow, but I am of the opposite point of view. Synopsys announced that it is delivering a comprehensive 3D-IC design solution that is included in TSMC's CoWoS™ (Chip on Wafer on Substrate) Reference Flow.

Zuken Innovation World in Newport Beach is just days away, but there is still time to register!

October 15-17, 2012
Hyatt Regency Newport Beach

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The conference includes two full days of presentations from Zuken experts, partners and customers.

• North America Power Utility implementation of E³.series (Hydro-Québec)
• World-class Silicon & Development Tools for Intelligent Embedded Connected Devices (Intel Corporation)

Kilopass Technology announced Gusto-2, its second generation of code storage products, to serve the increasing numbers of new system-on-chip (SoC) designs for instant-on mobile devices. Gusto-2 is available for SoC designs targeted for 2013 Q1 fabrication. It will initially be enabled on the 55nm and 65nm logic processes at IDMs and mainstream pure play foundries with enablement on smaller process nodes following.

One of the common characteristics of EDA companies is that most often the engineering teams are managed by hardware engineers. The result is that during product development much attention is paid to the problem to be solved and less emphasis is given to the software development methodology used. This to me is the core message of a presentation given at UC Berkeley by two staff members of Blue Pearl Software.

Calypto® Design Systems announced that Core Logic Inc., a fabless semiconductor manufacturer, has adopted PowerPro CG as their primary power optimization tool for designing their complex system-on-chip (SoC) products.

In a strange twist of reality I learned of the proposed acquisition of EVE by Synopsys because of a legal maneuver by Synopsys. It is not possible for a party to sue another party unless the first party has a material reason for the legal action. Thus the fact that Synopsys filed a Complaint for Declaratory and Injunctive Relief against Mentor Graphics on the subject of the legal proceedings that Mentor initiated months ago against EVE is an indication that Synopsys now would be materially damaged by the legal battle in the emulation business.