Real Intent, Inc. announced version 2.0 of its Ascent Lint tool for early functional verification. It adds 60 comprehensive rules including new FSM checks, while maintaining its analysis speed of up to 450M gates in less than one hour, with no need for hierarchical processing. Real Intent also added Verdi3 support for integration to this industry-leading debug platform from Synopsys.

Kilopass announced that its NVM IP is the first antifuse technology to achieve successful test chips on TSMC’s 20nm process. Analysis of the test chips containing Kilopass NVM IP memory modules validated manufacturability, process control tolerance and cell programming characteristics.

Kilopass Technology Inc. has announced the validation of its anti-fuse XPM (eXtra Permanent Memory) NVM IP as "Ready for IBM Technology" in the IBM 65nm 10LPe (low-power enhanced) process. Kilopass' XPM family provides up to 1Mb of storage capacity for portable device SoCs (System on Chip) that need the lower standby power consumption the IBM 65nm 10LPe process provides. Kilopass has successfully completed 1000 hours of High Temperature Operating Life (HTOL) and 1000 hours of High Temperature Storage Life (HTSL) per JEDEC 47 standard qualification on the IBM 65nm 10LPe process with no failures, thus assuring designers of at least 10 years of operating life for the XPM NVM.

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012. The all day workshop which following the tradition of Silicon Valley will start at 9:30am to give time for everyone to battle the traffic, will end at 5:00pm. The workshop will be held in Building 10 at the Cadence campus, 2655 Seely Avenue in San Jose.

Shakeel Jeeawoody, VP of Marketing at Blue Pearl Software, published a paper that describes a technique developed by his company to significantly improve the inter block analysis for complex designs. The technique is called Grey Cell Methodology.

Increasing design complexity is posing heighten verification complexity. Most of the consumer electronic products that are pushing vendors toward state of the art processes require real time responses. These applications cannot be debugged using software based tools. Thus the use of FPGAs for SoC verification has become the norm.

In the last two weeks both Synopsys and Tektronix have introduced new powerful verification solutions to aid engineers developing SoC devices.

One of the greatest values of a User Group is the ability to network with other users and compare the methods used with various tools from the vendor. The Jasper Users Group meeting will be held on November 12 and 13 at the Cypress Hotel in Cupertino, CA. The gathering will be especially interesting to designers, verification engineers and engineering managers. Attendees from around the world to share the latest verification best practices.

Amy Clements wrote the latest Zuken blog reporting on an analysis of the E³ series electrical CAD software. Jason Brett, who teaches electronics and material sciences in the Technology Teacher Education Program at the British Columbia Institute of Technology is the reviewer.

You can read the details by following the link in the Zuken box on the right.

The Blue Pearl Software Suite works with the Xilinx Vivado Design Suite running on Windows platforms. It includes linting, CDC analysis and automatic SDC generation. Its generated SDCs automate the synthesis and place and route phases of FPGA design implementation, and reduce iterations and overall design time. Its Visual Verification Environment makes it easy to use.

Zuken is not a frequently mentioned when I ask people in the industry to give me names of companies that are at the leading edge of our technology. Yet the company is a major player in the PCB market, second only to Mentor according to Gary Smith. The reason for this lack of knowledge rests, I believe, in the nature of the company. Zuken is a Japanese company with major research and development assets in Germany as well. This, I believe, justifies the reserved approach to the market. Zuken does not promote itself with the high profile events of its competitors.