Having been a long-time DVCon attendee (even back in the “HDLCon” days) and presenter even before becoming the Technical Program Chair, I continue to be impressed with how the technical papers so accurately reflect the current state-of-the-art, and future trends, of the design and verification industry. Now, some may argue that this is a bit of a “chicken-and-egg” situation, but I’ve always believed that the major value of a conference like DVCon is the unique opportunity it affords for engineers to learn from each other about emerging techniques and new technologies. In some cases, the most valuable lessons actually may be about what not to do.
The “hot topic” this year seems to be in the area of low-power design and verification. In addition to being discussed in the Keynote address by Moshe Gavrielov, Executive Vice President and General Manage of Cadence’s Verification Division, low-power will be the subject of a lively panel discussion on Thursday, moderated by the esteemed Richard Goering of EETimes, as well as an embedded tutorial session on Friday. Clearly, this will be a pressing issue in the industry over the coming year, and we hope that these discussions will shed some light on the issues surrounding it.
This year, we’ve taken the forward-looking approach to a new level by including two new sessions on Advances in Research in the EDA industry and academia. With topics ranging from transaction-level assertions and synthesis to platform-based design and RTOS modeling, these sessions promise a compelling look at the future of our industry. These sessions were organized with the goal of attracting tool developers, leading-edge engineers and other visionaries and pioneers to see what’s happening and offer their insights as well.
In another move to expand the technical program, this year we’re offering five sponsored tutorials on Wednesday, up from four in previous years. Over the years, these tutorial sessions (which are free to full-conference registrants or may be attended by exhibit-only registrants at a fee of $50/session) have proven to be of consistently high quality, especially in the depth of technical information provided with a minimum of “marketing fluff.” The one common theme running through all of the tutorials is the practical application of advanced verification technologies, from transaction-based testbench environments using either Mentor Graphics’ Advanced Verification Methodology (AVM) or Synopsys’ Verification Methodology Manual (VMM), to formal verification tutorials, one sponsored by Cadence Design Systems and the other by Jasper Design Automation and Sun Microsystems. The fifth tutorial is sponsored by the Open SystemC Initiative (OSCI) and will cover the new TLM2 transaction-level modeling standard.
A second technical panel on Friday will discuss the concept of “Blended Coverage” – the multi-dimensional problem of gathering and analyzing different types of functional and structural coverage used today. The panel is organized and moderated by Harry Foster, one of the true visionaries in the industry, and includes a distinguished panel of verification professionals who will offer their perspectives on this important topic. As methodologies and tools continue to improve, the ability to manage all of the coverage data, whether gathered from simulation, formal verification, or other tools, is certain to be central to your ability to successfully know when you’ve actually completed your verification. You won’t want to miss this one.
The technical paper sessions are extremely strong this year, and I’d like to take this opportunity to thank everyone who submitted a paper for consideration. The fact is that the Technical Program Committee had a hard time selecting the final papers from many high quality abstracts we received. In the end, we were able to put together a very valuable and informative set of sessions, ranging from SystemVerilog for design, assertions and DPI (separate sessions), to SystemC in action, formal verification and a session on Real-World Verification Applications, which examine actual case studies of real verification problems.
And, of course, Thursday wouldn’t be complete at DVCon without the infamous John Cooley “Bigwigs Panel.” Remember to keep your eyes open for John’s invitation to submit questions to make the panelists squirm, then come on down and watch the fun.
I invite everyone reading this, especially those of you on the front-lines of design and verification, to register and attend DVCon on Feb. 21-23 at the Doubletree Hotel in San Jose. I’m sure you will find these three days to be chock-full of useful information that you can take back with you and improve your current practices. If you get back home and find just one more bug (or avoid designing it in the first place), the conference will have paid for itself and we’ll all be able to bask in the glow of a job well done.
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