Phil Hester, CTO of AMD talked about "An industry in transition: opportunities and challenges in next-generation microprocessor design" at the International Conference on Computer-Aided Design.

Over time, semiconductors in computers have improved performance and reduced costs by orders of magnitude. By the '90's some microprocessors like the DEC Alpha were able to perform about 10 percent of the processing of a supercomputer at 1 percent of the cost. Between the '80's and '90's, graphics performance went from simple wire-frame drawings to textured surfaces. By 2002, a graphics processor included the capabilities of a general purpose computer and greatly exceeded its compute performance.

As processing power has increased to the 150 to 200 Gflop range, the depiction of physical attributes is no longer the task of the CPU, but is entirely within the GPU. Since '04, graphics processors have outperformed general purpose processors by a factor of 50. This increase in performance and programmability greatly exceeds the performance of a '90's supercomputer, and now the CPU has to work full time just supplying volumes of data to the GPU.

Processor functionality and performance have improved by an order of magnitude every 15 years. Now we are approaching the era of the petaflop (1015 floating point operations per second) on the desk. This performance is a result of the increasingly parallel architectures in the latest processors. A candidate architecture is a computer with over 1000 processors. The difficulty is getting that many CPUs and co-processors into a system within the power and memory access constraints.

This trend in integration is not new. In '89, the PC used a 286 processor and if you needed additional numerical processing, added a 287 math co-processor. By the 486 generation, the floating point unit was integrated into the main CPU. Other enhancements included MMX in '97, SSE in'99, and a move to 64 bit in '03. By '08, the 3-D graphics functions will be included. This integration will address the energy efficiency issues and will enable petascale computing. The step function improvements will change the performance/watt/cost metrics for computers.

Current projections are for the petascale computer to be binary compatible with x86 instructions, and will use a heterogeneous mix of cores. The large number of parallel cores and integrated GPU will share a cache. The design will use a modular approach, with extensive reuse of IP to allow optimal fit to the end use. Time to market and clear classification of end users will be the principle challenges.

The solutions will lay with a pick and choose from a menu approach to add the quantity and type of processing functions to the chip. All future chips will be increasingly multi-core and the software will be much more multi-threaded. The CPU and GPU will become an integrated unit to reduce power and latency in the system. In conjunction with the petaflop on a desk processor arrays, professional-grade CAD will be enabled at the home by the networking of many such systems.

The supercomputer on the desk is almost here. The next generation x86 systems will be capable of teraflops and the following generation will hit the petaflop range. The biggest constraints are power and memory—both bandwidth and the overall structures to keep the pipelines full. The greatest need is to find a balance of processing power, electrical power consumption, and total costs while achieving this incredible computing performance.

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