Sept. 28, 2006—Chartered Technology Forum, Santa Clara—Jim Hines, Dataquest analyst, moderated a panel on "beyond 45 nm: will bulk CMOS still dominate?" that looked at the likely technology implementations after the 45 nm node. The panel included Lisa Su, vice president of semiconductor research and development- IBM, L.C. Hsia, senior vice president of technology development-Chartered, H.K. Kang, vice president of technology development-Samsung, Nick Kepler, vice president of process technology-AMD, Franz Neppl, vice president of engineering-Infineon, and Matt Nowak, director of engineering VLSI technology –Qualcomm.

In response to the first question, "is CMOS scaling reaching practical limits?" the panel mostly agreed that a lot of work needs to be done, but CMOS will be around beyond 32 nm through a combination of optical and materials enhancements. Neppl added that although there are still several generations of silicon to go, the real question should be "what is the real value proposition for the silicon advances?" and whether companies should push the technology and integration capabilities, since there may be other limits in how much integration is reasonable or necessary versus how much is possible.

Kang demurred and asked what is the motivation is for change. The economics are the drivers for the changes in technology and projections for both costs and technical hurdles dictate that a single company cannot continue to advance the scaling more than one more silicon generation. Nowak noted that the planar technologies are limited, but 3 dimensional topologies may extend the ability to improve density and performance. Unfortunately, the rules don't scale linearly and the industry cannot continue to get 25 to 30 percent improvements per year. If the material, topology, and architectural changes are insufficient to continue Moore's law advances then the industry will look for other solutions that are cost effective. If no alternatives are developed, then the industry will be stuck in a dead-end.

The second question concerned the source for innovation and the drivers for change as fundamental limits appear. The panelists generally agreed that materials and architectures will dominate the changes. Su noted that greatly increased interdisciplinary work is needed to make architectures map better to newer processes and their new constraints. Kang postulated large changes in standard practices in the near future as the current stopgap measures for power and DFM eke out the last of their minimal gains. If it is possible to integrate high-k dielectrics into the standard process, then more materials changes will be viable. Kepler noted that materials changes may not be the panacea, since the easy changes are already done. Future process and design functions will require close communications across process, design, and architecture groups to bring about advances beyond the easily foreseeable needs.

Although the IDMs may have a short-term advantage in the next generations of processes, the changing business models and increased willingness of the fabs to share manufacturing and modeling data will level the playing field fairly quickly. In addition, the new business models will require the designers to share more of their design intent with the foundries to ensure successful silicon. The largest fabless companies will work closely with their foundries to define the next generation process and device requirements. The increased level of interactions will create a virtual IDM relationship in the industry.

The next question challenged the basis for next-node progression; since 98 percent of the industry is using processes greater than 65 nm, is the concern about sub- 45 nm processes irrelevant? Nowak agreed that the industry is seeing an increasing dichotomy—fewer companies are moving to the latest process due to affordability issues. If the production costs for a process don't drop at least 25 percent per process, the next process in not viable. When the costs of a process approach parity with the previous generation, the era of scaling and doubling is dead. Kepler agreed that most companies don't need or cannot afford 65 nm, and definitely don't want to try 45 nm. Only the very largest volume users and very specialized applications will ever need to consider the sub- 45 nm processes.

Neppl concurred that the up front costs are a growing barrier. Increasing integration will go on through vehicle like programmable platforms that can minimize the threshold for volume by splitting a wafer run for different functions. Su added that the costs for lithography and other infrastructure will be a major hurdle for both the IDMs and the fabless companies with their foundry partners. Currently there is an applications pull for leading-edge technologies, but if the cost crossover for manufactured parts does not happen, the 32 nm node will be delayed significantly.

Since most of the industry is on older processes and not moving quickly to newer processes, users can expect to see processes like 90 nm have a manufacturing lifetime of over 10 years. Hsia observed that the first wave of users for a process is the largest customers. Later, the smaller companies adopt the N-1, N-2, N-.. processes as their need for increased integration outpaces the capacity of the older generation. The fabs will need to maintain a large technology base to supply the needs of all of their users.

And finally, "is bulk CMOS dead beyond 45 nm?" resulted in predictable answers. Kepler stated that power is becoming a primary limiter, so Silicon on Isolator (SOI) is better than bulk for leakage control. Kang noted there was no demand for bulk at 90 nm, so SOI is the only viable technology going forward. The design community needs a new and complete eco-system to enable higher demand for SOI. Nowak stated that SOI must be cost effective or there will be no opportunity for smaller process nodes. The good thing is that there are many ways that SOI is more cost effective than bulk, such as 1-T RAM cells with a floating body. Another benefit is that power-control architectures are easier to implement when you have larger design capacities on chip. Hsia added that SOI is good for high temperature operation. Also, because there is no latch-up, a user can shrink the spacing between the P and N devices.

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