July 25, 2006, DAC San Francisco

Synopsys hosted a breakfast to discuss "Escape from analog Alcatraz through Open Access" here at DAC. Chi Foon Chan, president of Synopsys opened the day with some introductory comments on the coming changes in analog and mixed-signal design. He noted that the latest designs need to address high density digital while interfacing to high-speed data communications, which are analog. The latest Synopsys efforts are in adding power aware extensions to existing standards to enable and facilitate analog designs.

The challenges for analog designers is that their design productivity has not changed much in the past 30 years, certainly not even close to the levels of digital design. Unfortunately, most designs now include some analog or mixed-signal components. If you include the PLLs, all designs include analog components. One possible solution to the analog bottleneck is to use OpenAccess (OA) enabled tools. OA enables fairly easy mix and match tool flows which include best in class tools for improved productivity. The standard data formats and open API allow easier data exchange and improved interoperability within the analog tool chain.

In today's designs, analog may take up to 20 percent of the area, but contributes 500 percent of the risk. This is a big problem. As designs become larger, the costs increase to greater than $50 million and the high-speed interfaces are the most difficult section. Some designs are going through 12 turns to get the analog sections working properly. Unfortunately, the market windows and finances don't allow for more than 2 turns and a ceiling of $40 million development cost.

To make things even harder, the growing size of analog designs, teams, and complexity is creating a gap between the specifications and final silicon. To solve the problems, of the design-to-specification gap, major changes in tools and methodologies need to occur. An existing partial solution is the development of process design kits (PDK) that contain the analog building blocks and fab analog libraries. The PDKs and their parameterized cells (P-Cells), unfortunately are not portable and have the additional problems that they are developed early in the process from memory technologies, and not the analog process modules.

Therefore, the industry needs to have transportable PDKs based on SKIL type P-cells and developed in an open language, such as Python. The PDKs need to include layout generators and eventually will need to work with language-based tools. By going this route, users would have orders of magnitude in productivity and will also obtain design rule correct-by-construction layouts, reducing the need for the many spins. The tools should be based on SI2's OA to reduce the need for splintered developments.

One of the big issues for designers is the change in design content. Upwards of 80 percent of designs now include some mixed-signal components, and SoC designs are moving to multi-core architectures. In addition to the analog and mixed-signal components, the designs are applying digital corrections to the analog functions, making large-scale mixed analog-digital simulation an important ingredient in any new tool package. Many designs are now faced with the challenge of simulating the complex interactions of analog and digital subsystems with few viable alternatives. The fast Spice tools still cannot handle the mixed timing resolution coupled with the large volume of digital and analog transistors. To make matters even worse, the latest processes need to be simulated at high precision or any work with parasitic elements becomes purely guess work.

The analog portions need to closely couple the electrical and physical views, since the two highly interact. A fast parasitic simulation would help move the analog design from a mostly manual process to a more highly automated one. One result of a much faster simulator would be the development of automatic analog floorplanners, placers, and routers. A tightly coupled layout and schematic editor facilitates rapid incremental changes, while a language-based methodology together with analog primitive cells enables more extensive design exploration.

In addition, the analog portions of the design need to follow the digital and use more reusable IP blocks. The continuous redesign of functions is not very useful nor is it very productive. Analog IP would empower tool makers to develop analog electrical synthesis as well as a design database that incorporates all relevant parameters including design intent. For designs in the wireless domain, a system-level tool such as Matlab is necessary. It must have the ability to create hierarchical representations down to the analog Spice level.

Critical functions for the next generation tools include a fast analog Spice simulator at least 100 times the speed of the fastest Berkeley Spice. Tightly coupled is a fast digital Spice that is 10 k times the speed of Spice and the following functions: harmonic balance, EMI (electrical-magnetic interference), circuit synthesis and optimization. In addition, the schematic and layout tools have to be highly interactive. All of the functions would be coupled together by an extension language like Python, since tkl, perl, scheme, or other scripting languages cannot handle the various data and structural types without great effort in programming. The ideal tool suite should be modular, so functions can be changed or replaced without a major retooling effort.

Since all of the existing tools need to be replaced, new features should include automatic propagation of changes across tool and data boundaries. The switch between simulators should be seamless and transparent to the user, whether the user needs a transistor-level tool or an algorithmic one. Debug tools have to cross probe across the tools through a tightly coupled database.

How should these new tools be developed? A modern software development process should use small teams doing parallel work. The next-generation tool developers need modern software engineering practices and languages, not C and Unix. EDA companies have been slow to move to C++ or other object-oriented languages, modular design with highly reused software components. The underlying software infrastructure should be COM-like to allow plug and play components and reconfigurable flows.

The danger of not changing in time is to miss the next markets. Since 1999, the open source software movement has made significant contributions to the software design process. An open database like OA can unify tools from all EDA vendors, making proprietary databases expensive baggage that users may not accept. OA is the next generation Cadence (supplied) database that start-up companies are adopting as their native database. This existing database allows the start-up companies to spend their precious resources on differentiated tools and functions rather than on database development, possibly accelerating their market entry by a year.

OA helps in setting standards and interoperability across tools. It is good for users who can ask for OA components and reduce the internal CAD workload for tool and database cross functionality. The CAD groups can put their efforts into better customized flows rather than working on multiple translators and scripts for data exchange. The interoperability standards still need work, but overall the single database is working.

Philippe Magarshack of ST Microelectronics described the existing and desired environment for analog and mixed-signal designs that his company lives with. The current tool set looks like a grab bag of tools and database from many vendors and the internal CAD developers.

The tools have to address RF, analog, and vast ranges of mixed-signal designs. After the designs are finished in the simulations, another potpourri of tools gets invoked for the various physical verification tasks. All of this design work requires large amounts of data translation and tool interface development to complete the projects. To compound the problems in the tools, the designs are created by multiple design teams and the IP blocks come from several different design groups or companies with different CAD environments and flows.

The analog designs require better data standards. Digital has many standards to address the various facets of design, but the analog side only has Spice. To date, the analog EDA vendors have stayed with proprietary languages and standards that are drivers towards less innovation. As the digital world becomes more analog, and RF-SoC and RF-SIP designs become commonplace, the need for higher efficiency analog CAD demands much more innovation.

As a first step, the PDKs need to be standardized. Today, each tool, even from the same company, places the same data into incompatible tech files. OpenAccess helps by formalizing and standardizing the data, but many more parts of the data flow need to be changed. The reality is that analog is not like digital. Analog designs need hierarchical schematics and parameter passing to address the high complexity in the designs. At the same time, analog designs have to use very complex P-cells for components like inductors and capacitors. Even when the vendors use the OA database, their implementations are not compatible and require extensive pre-and post-processing to exchange data.

The emerging SIP (system in package) technologies are pushing developments into orthogonal directions. Design kits need to include more functions and accuracy to enable the design complexity in today's designs. The passive component design and modeling must now include 3-D and substrate effects while electrical and geometric measurements generate reasonably compact models. And the substrate technologies themselves are changing, calling for more exact algorithms and models.

The highly desired goal is to have all tools work with any other tools across a common database. The database holds a unified technology description and a unified design description. The tool flow would start from a single language description of the design which would be redirected to various tools for analysis, optimization, and verification. Feedback from the digital block flow goes back to the original executable and into the analog portions as needed. All of the physical design functions would reside on an OA base, with translations to other formats as needed. The final verification would use a combination of Spice, HDLs, and GDS-II (or Oasis in the more distant future) for design confirmation.

The only way to achieve this goal in tools is to have everyone standardize to an open platform. Designing an RF/analog/mixed-signal circuit in the next generation of processes, starting at the 65 nm node, will require transistor level simulations. To address the process variability, the simulation models must be based on statistical process descriptions and correlation with production characterization. These models must have highly accurate extracted parameters and some new tools are coming on-line to address the device performance issues. The tools set must also be able to explore new effects and model the technology and process to track the changes in process over time.

In conclusion, analog/RF needs a database standard and OA is a good starting place. However, OA needs to get standards for process-related information and P-Cells to allow true design interchange including simulation and test benches. The challenges in analog design require dramatic increases in designer productivity that can only be achieved through innovation. The needs of the industry require capabilities for better verification, and reuse through resizing and layout optimization. Architectural evaluation requires the ability to make analog/digital/RF tradeoffs only possible through co-design, not only at the SoC level, but also as a part of a SIP.

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