May 17, 2005, Santa Clara—Alireza Kasnavi, R&D manager for Synopsys presented a technical update to the Composite Current Source (CCS) models for timing analysis here at the 17th Synopsys interoperability forum. This set of models is becoming necessary in designs migrating to 90 nm and smaller process nodes as former secondary effects are growing in significance and consequence.

The decreasing supply voltages and signals, coupled with increasing analog characteristics is making changes in timing models necessary. The design techniques needed to address the issues of timing, noise, power consumption, and supply grid I-R drops are calling for more models covering a wider spread of process, voltage, and temperature (PVT). A large and complex design might need tens of PVT combinations to address a majority of the design, and the idea of a worst case process corner quickly loses meaning. To make things even harder, the number of cells in a library is also growing.

As the processes become smaller, the ability to transfer the designs into manufacturing increases in difficulty as a higher order function of the number of PVT combinations. The challenges are exacerbated by the increased interdependence of the parasitic effects. In the past, a designer could get away with separate models for timing, power, and noise, so the characterization and modeling of the effects could also be separate. Now, the deleterious effects are highly interrelated. Timing is affected by noise, voltage, temperature, and signal conditions, I-R drop changes with power and switching activity, etc.

As the dynamic effects become more complex and interrelated, the ability to model the actual device performance becomes more difficult. The models must encompass process and device variability, dynamic interconnect impedance, temperature and voltage effects, and even the effects caused by the input and output signaling environments. At the same time, the models have to run on existing tools and have to maintain the ability to scale for variability and capacity. The conundrum is that the models need to change to reflect the need for greater accuracy without increasing run times in the (soon to be) merged analysis engines.

Synopsys has improved the CCS timing models to capture more of the dynamic effects. The first steps require new and more complex characterization of the devices and their operating environments. The models now use input and output current waveforms and a piecewise linear set of capacitors to match delays and slew rates for the beginning and end of transitions. Noise characterization is actually faster and more accurate than the non-linear delay tables (NLDM), since the point measurements can be interpolated and extrapolated for near neighbor sets of conditions rather than needing separate characterization. All models are derived from fairly simple primitive 1 or 2 level cells like inverters and 2-input gates.

To model power effects, even with multiple supply and ground rails, engineer use the same characterization conditions as the timing models, so overall characterization efforts are reduced. For the sub-90nm processes, the models must also include static leakage currents. The models enable voltage and temperature scaling of the transformed current sources and are closer to SPICE than other models. The design of the models allows interpolation of the models between libraries at a single PVT point.

To ease adoption of the models and characterization requirements, Synopysis has added new tools and utilities to the Liberty modeling suite to improve overall model fidelity and ease of development. The increased accuracy enables the designer to reduce guardbands and achieve greater performance from their designs.

Mehmet Cirit, president of Library Technologies, feels that the models are only accurate at loads much larger than the native device parasitics. The piecewise linear approach allows extrapolation and interpolation in PVT areas in close proximity to the measured points, but are not accurate when input and output loads are close to those in the circuit, or if more than one variable is changed. He has seen variations of 20-30 percent from SPICE in the CCS models for some of their existing and emerging libraries.

To comment on this article send email to:gmoretti@gabeoneda.com