The announcement by Mentor Graphics of the release of the Questa 6.2 verification platform included a new technology module called Advanced Verification Methodology or AVM. The AVM is an open, non-proprietary verification methodology, implemented in Both SystemC and SystemVerilog, that supports a true system-level-through-RTL design and verification flow. In contrast to other verification platforms on the market, AVM is independent of any other proprietary products and thus can be used with verification products from other EDA vendors. Designed from the ground-up to take advantage of the new verification capabilities in SystemVerilog and SystemC, the AVM features an object-oriented coding style to reduce the amount of testbench code and a modular architecture to enable reuse. Available under a standard open source license, the AVM may provide the engineering community with a standard multi-lingual verification environment.

The AVM uses a layered architecture. The lowest level of abstraction, the one that connects to the design under test (DUT) via its pins contains transactors, like drivers, monitors, and responders. This layer is protocol specific in the sense that it implements the communication protocol between the DUT and the target execution environment. The level above implements the test environment and contains stimulus generators, constraints, and both master and slave test modules. The two layers communicate via transactions. The third level of abstraction is the analysis level. It contains coverage collectors, scoreboards, performance analyzers, and golden models. It communicates with the environment level through either untimed or partially timed transactions. The upper level of abstraction contains the test controller that manages the verification through untimed transactions with the analysis layer.

The AVM provides libraries of base classes for both languages and modules for SystemVerilog. The communication mechanism between verification components in the AVM uses TLM interfaces as defined in the OSCI (Open SystemC Initiative) TLM-1.0 standard, implemented in both SystemC and SystemVerilog. By standardizing communication between components, users are free to focus on the component behavior to support constrained-random stimulus generation, functional coverage, scoreboarding, and more. Since all components utilize the same standard interfaces, the components themselves are reusable across multiple projects providing substantial productivity gain for the user. Productivity is further enhanced since the focus on TLM interfaces makes it easier to develop verification components at higher levels of abstraction, simplifying coding, debug, and test.

By mixing classes and modules, the AVM has the advantage of being easy to connect directly to an RTL DUT, while retaining the needed flexibility and configurability. In addition to simplifying the DUT connections, the use of modules allows AVM-compliant components to contain assertions to check behaviors and collect coverage information, which can be communicated to the rest of the testbench via TLM. The use of TLM, implemented in both SystemVerilog and SystemC, allows the exact same concepts to be applied to system-level architectural models written in SystemC as to RTL and gate-level models in SystemVerilog, Verilog, and VHDL.

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