Novas Software, Inc announced its new family of Siloti™ Visibility Enhancement (VE) products to address the problem of decreasing visibility into the functional operation of complex ICs during late stage verification and system validation. In early simulation runs, engineers achieve full visibility by dumping as many signals as needed. But in full-chip regression simulation, the number of signals is so large that dumping everything becomes prohibitively expensive, and users must be selective. This problem becomes even more severe in emulation, prototype, and actual-chip situations because access to signal data is only through logic structures that must be inserted into the hardware.

The Siloti visibility enhancement technology speeds the process from discovery of erroneous behavior in late stage verification and validation to the understanding and repair of its causes by: analyzing limited signal data; automatically deriving missing information; and correlating complex low-level representations with register transfer level (RTL) descriptions.

The first two Siloti Compositions

Novas is delivering these visibility enhancement capabilities through a series of application-specific products, starting with the Siloti SilVE™ and SimVE™ offerings.

These first two Siloti products work with third-party simulation, emulation and FPGA-based prototyping tools, as well as emerging DFD tools and test environments. They are also tightly integrated with Novas’ Verdi™ Automated Debug System to bring RTL debug to visibility-challenged environments.

The Siloti SilVE product works with emulators, prototypes, and DFD-enabled chips to optimize observability of signals. It first compiles the HDL design and performs formal analysis to determine which signals are essential. This information can guide insertion of access points or probes into the device so that the required signal data can be obtained during emulation or operation of the prototype. The Siloti abstraction correlation and data expansion engines then work together to automatically map the low-level structures of the actual chip up to the RTL level and expand the dumped data to fill in the gaps for full visibility. Novas is awaiting patent approval on this unique process of providing RTL-level visibility for chip-level data.

The Siloti SimVE product works with standard HDL simulators to make regression simulation more efficient. With current methodologies, engineers often run multiple regression simulations, first without dumping any signal data, and then again when a problem is discovered dumping only data they estimate is necessary for debug. If they guess wrong, another iteration is required. By deploying an optimized methodology that limits dumping to a small but critical subset of signals, SimVE users can achieve full-chip functional debug with a single regression run and minimal impact on simulator performance.

Both the Siloti SilVE and SimVE products are tightly integrated with the Novas Verdi debug system, such that the Siloti data expansion engine is automatically invoked when users request visualization or tracing of data that was not dumped.

Other Companies ad the Works to their repertoire

EVE announced that its hardware-assisted verification platform has been integrated with the Siloti™ SilVE™ Visibility Enhancement product. This integration builds upon earlier interoperability efforts between the two companies that links EVE’s ZeBu (Zero Bugs) with the Novas Verdi™ Automated Debug System.

The combination of EVE’s ZeBu and Novas’ Siloti products enables engineers to achieve full visibility into the functional operation of complex designs for debug of problems found through emulation. The gate-level netlist is fed into the SilVE environment and analyzed to determine the essential signals needed for the entire design or specific logic area of interest. ZeBu then sets probes on the targeted registers and writes out or “dumps” the data for these essential register signals. This chip-level data is processed within the SilVE environment to calculate the missing values on-demand, providing ZeBu users with full visibility into design operation and automated debug capability at the RTL level with Novas’ Verdi debug system.

Furthermore, Novas Software, Inc. has joined the Altera ACCESS Program for integrating and supporting complementary design technology. The companies are collaborating to increase signal visibility for easier debugging of complex systems on a programmable chip (SOPC) and FPGA-based product prototypes.

The two companies will initially work together on the interoperability between the Quartus II development software’s SignalTap II embedded logic analyzer and the new Siloti™ Visibility Enhancement (VE) products introduced separately today by Novas. The SignalTap II embedded logic analyzer is a system-level debugging tool that allows designers to observe signal data via gate-level probes. The Novas Siloti SilVE™ product optimizes the visibility of the signal data by determining the essential set of probe points required, and then expands and correlates the data to provide full visibility of all internal signals at the register transfer level (RTL) for debug. The combination of these capabilities will replace guesswork and multiple analysis-debug iterations with a predictable, high visibility debug methodology.

Finally, DAFCA, Inc., a provider of on-chip reconfigurable debug infrastructure that enables the rapid discovery and diagnosis of in-silicon functional errors, announced support for the Siloti™ SilVE™ Visibility Enhancement (VE) product.

DAFCA’s ClearBlue™ instrumentation studio is a seamless part of the synthesis flow. It inserts reconfigurable instruments at RTL or Gate Level for post-silicon use. DAFCA’s ClearBlue debug environment offers a wide spectrum of configurable analysis choices, including trace buffers, logic analyzers, cross-triggers, and assertion-based debug, that all feed directly into Novas’ FSDB (fast signal database) interface.

The complexity of third-party cores, coupled with ambiguous specifications and unanticipated use models, makes post-silicon debug the least predictable and most expensive part of the design flow. Delays from in-silicon functional errors are the most lethal to silicon vendors. The DAFCA and Novas product integration will provide a comprehensive post-silicon debug solutions, allowing customers to dynamically “dial in” the intervals they want to see, and identify the signals that need special attention. Moreover, the combined solution removes the classic trade-off between observability and performance.

Pricing, Availability, and Alexander Siloti

The Siloti SilVE and SimVE visibility enhancement products are immediately available starting at $65,000 U.S. list for annual subscription licenses. For more information on Novas’ Siloti solutions, visit www.novas.com/Solutions/Siloti/.

If you don't already know about Siloti:

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