Jim Solomon described the requirements for "Next generation EDA" in his keynote address at the Synopsys Interoperability forum. One of the big issues for designers is the change in design content. Upwards of 80 percent of designs now include some mixed-signal components (all designs if you consider a PLL in every design) and SoC designs are moving to multi-core architectures.

Many designs are now faced with the challenge of simulating the complex interactions of analog and digital subsystems with few viable alternatives. The fast Spice tools still cannot handle the mixed timing resolution coupled with the large volume of digital and analog transistors. To make matters even worse, the latest processes need to be simulated at high precision or any work with parasitic elements becomes purely an educated guess.

In addition to the analog and mixed-signal components, the designs are applying digital corrections to the analog functions, making large-scale mixed analog-digital simulation an important ingredient in any new tool package. As an example, a 802.11g wireless Ethernet chip from Atheros uses about 100k logic transistors in a feedback loop with 10k analog transistors. This design is not something that neither Verilog-A nor Spice can easily handle.

Another design, from TI, is an algorithmic mixed-signal radio. Its correction loop includes 150 k logic transistors while the analog section handles everything including the RF. This design needs to be simulated in the time domain rather than the frequency domain because of the RF sections. (Usually RF is done with harmonic balance). A minimum requirement is something at least two orders of magnitude faster than the fastest Spice available.

A third example of a difficult design is a 7 channel audio amplifier with digital equalizer and other functions from D2 Audio. This design uses over 10.7million logic transistors to control the 50 watt per channel amplifiers. Due to the random logic, a fast MOS simulator cannot speed up the logic simulations, but the details of the power drivers require Spice accuracy. The lack of Verilog-A models prevents the use of a Verilog simulator for the circuit. This design needs speeds of 10k times the speed of Spice.

The analog portions need to closely couple the electrical and physical views, since the two highly interact. A fast parasitic simulation would help move the analog design from a mostly manual process to a more highly automated one. One result of a much faster simulator would be the development of automatic analog floorplanners, placers, and routers. A tightly coupled layout and schematic editor facilitates rapid incremental changes, while a language-based methodology together with analog primitive cells enables more extensive design exploration.

In addition, the analog portions of the design need to follow the digital approach and use more reusable IP blocks. The continuous redesign of functions is not very useful nor is it very productive. Analog IP would empower tool makers to develop analog electrical synthesis as well as a design database that incorporates all relevant parameters including design intent. For designs in the wireless domain, a system-level tool such as Matlab is necessary. It must have the ability to create hierarchical representations down to the analog Spice level.

Critical functions for the next generation tools include a fast analog Spice simulator at least 100 times the speed of the fastest Berkeley Spice. Designers also need a fast digital Spice that is 10 k times the speed of Spice and the following functions: harmonic balance, EMI (electrical-magnetic interference), circuit synthesis and optimization. In addition, the schematic and layout tools have to be highly interactive. All of the functions would be coupled together by an extension language like Python, since tkl, perl, scheme, or other scripting languages cannot handle the various data and structural types without great effort in programming. The ideal tool suite should be modular, so functions can be changed or replaced without a major retooling effort.

Since all of the existing tools need to be replaced, new features should include automatic propagation of changes across tool and data boundaries. The switch between simulators should be seamless and transparent to the user, whether the user needs a transistor-level tool or an algorithmic one. Debug tools have to cross probe across the tools through a tightly coupled database.

Jim Solomon observed that all design tools should go through a major updating every 7 to 10 years. The existing EDA tools are all over this age limit, and have evolved through hacking, code changes but not redesign of structures and algorithms, and through acquisitions. The costs of maintaining worn-out legacy code is huge, not only for the EDA companies, but also for the design teams that have to use marginal and non-productive tools for their work.

How should these new tools be developed? A modern software development process should use small teams doing parallel work. The next-generation tool developers need modern software engineering practices and languages, not C and Unix. EDA companies have been slow to move to C++ or other object-oriented languages, modular design with highly reused software components. The underlying software infrastructure should be COM-like to allow plug and play components and reconfigurable flows.

The danger of not changing in time is to miss the next markets. Since 1999, the open source software movement has made significant contributions to the software design process. An open database like Open Access (OA) can unify tools from all EDA vendors, making proprietary databases expensive baggage that users may not accept. OA is the next generation Cadence (supplied) database that start-up companies are adopting as their native database. This existing database allows the start-up companies to spend their precious resources on differentiated tools and functions rather than on database development, possibly accelerating their market entry by a year.

OA helps in setting standards and interoperability across tools. It is good for users who can ask for OA components and reduce the internal CAD workload for tool and database cross functionality. The CAD groups can put their efforts into better-customized flows rather than working on multiple translators and scripts for data exchange. The interoperability standards still need work, but overall the single database is working.

Another discontinuity that EDA developers need to address is the move to multi-core processors and multi-threaded computing. This change will affect design styles as well as the internal structures of the tools and databases. A multi-threaded process needs to address not only parallelism and concurrency but also data synchronization to ensure the threads don't get into a thrashing or deadlocked state.

The start up companies are ahead in developing OA native tools, except for schematics, and can overtake the industry leaders in supplying specialized, flexible flows. New timers, timing optimization, and synthesis algorithms will take advantage of the parallelism in multi-processor servers. The ability to reconfigure design systems in a modular fashion will enable application-specific methodologies that can work seamlessly from system- to transistor-level design.

To comment on this article send email to:gmoretti@gabeoneda.com