Wally Rhines, EDAC president, opened the evening festivities with some preliminary remarks. First, he described the make up of EDAC and noted that with 22 new companies joining the consortium in the past year, the net increase in membership was 2 companies. 20 companies disappeared through mergers and acquisitions or other fiscal actions.

Next, Rhines acknowledged the contributions of the various committees in EDAC and handed certificates of appreciation to the committee chair and vice chair persons of each committee. He especially noted the contributions of the export controls committee and their work on getting changes in regulations for export controls and their current progress in getting exemptions for encryption regulations for EDA companies.

As a part of the annual event, EDAC surveys the CEOs of its member companies to get a snapshot of the environment. This year, 29 of the 118 CEOs responded to the survey. In response to the question "what are the opportunities for growth", the answers included design complexity, DFM/DFY, innovation in methodology, ESL and demonstrating value to customers.

Answering "What are the barriers for growth?" the CEOs noted price wars, limited markets and target companies, reduced (R&D) budgets for EDA, reduced design starts, and inability to demonstrate value to customers. The company leaders expected staff increases in pre-sales support, R&D, post sales support, consulting services, and administration.

The CEOs expect growth in DFM/DFY, semiconductor IP, physical design and verification, CAE, and ESL and decrease in PCB tools. They have not been very close in forecasting overall industry revenue trends in the past few years, so this year's forecast of 5 percent growth in '06 and '07 should be taken with a grain of salt. There were some interesting comments about EDA and Silicon Valley which you can view at http://www.edac.org/events_presentations.jsp#2005kaufman.

Following Rhines' opening remarks, Richard Newton, Dean of Engineering at UC Berkeley presented the12th Annual Kaufman Award to Phil Moorby for his contributions to EDA through the invention of the Verilog hardware design language and its accompanying simulator. Moorby worked on HiLo, a logic simulator, and identified links between simulations and synthesis as significant for the next generation HDLs.

His work on the first version of Verilog enabled the ASIC revolution and was the first HDL to represent all levels of hardware design from switches to gates to registers within a single language. Algorithm development was one of the primary difficulties because of the need to address requirements from mathematics, engineering, and the underlying information technology structures.

On top of the challenges in creating a new language and simulator, the advent of the HDL language wars between Verilog and VHDL hindered development and user adoption. In addition, the requirements for a synthesizable subset of the language created new opportunities for language simplification while requiring additional development work in the language and simulator.

Moorby, like his Kaufman award predecessors, acknowledged the influences of many other people in his work. His initial efforts were influenced by Jerry Musgrave and Peter Flake on the early HiLo language and simulator, and later Prabu Goel, Simon Davidman, and Chi Lai Wang for their inputs while at Gateway. He noted that the development team made many contributions and even the sales force provided useful inputs for the Verilog language and simulator. Moorby recognized the effects and value of competition from people like John Sanguinetti and others, and welcomed their inputs when language was put before the IEEE as the 1364 standard. Moorby worked on Superlog HDL which has become the basis for the SystemVerilog language as another IEEE standard.

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