The Fabless Semiconductor Association (FSA) Expo included a panel discussion on "Collaborating effectively on the rocky road to DFM". Handel Jones of IBS introduced the topic and moderated the panel.

Jones noted the migration from the 90 nm to the 65 nm process node is being slowed by the DFM (design for manufacturing) issues associated with the ramp on the 90 nm process. The 90 nm process had no major changes from the 130 nm process, but is now running about 18 months behind schedule for adoption in designs. Device leakage is the major factor in the delay, which demonstrates the need for closer coupling between design, CAD, reticle processing, and semiconductor manufacturing.

Today, most DFM had a yield perspective, with projected yields being a function of total area. However, the increase in leakage and the corresponding increase in power have resulted in the costs for manufacturing a die increasing as a percentage of the total cost. Manufacturing a 90 nm wafer is now 60 percent of total manufacturing costs. The other side of the economic coin is that the margins per part are going down. To exacerbate the situation, a fab now needs about $5 B in revenue to break even. These costs are forcing the number of IDMs (independent device manufacturers) to drop as many companies are not able to keep up with the economic requirements.

As processes move to 90 nm and below, the gate capacity per die goes up dramatically. The average gate count per design, however, is not increasing as quickly, so the cost per gate is not going down as much as necessary for continued process evolution. In the past, the cost per gate dropped by a factor of 2 for each process node. Now it is down to about 1.2 times. R&D investments are up to about 16 percent of revenues across the industry with product development accounting for a total of about 10 percent of revenues in an attempt to improve the cost per gate function.

The panel then offered their statements. The panel was comprised of Lance Glasser of KLA Tencor, James Healy of LogicVision, John Kibarian of PDF Solutions, Marc Levitt of Cadence, V. K. Raman of Qualcomm, and Anatha Sethman of Synopsys.

The first question to Glasser was about inspection. In response, Glasser observed that the 65 nm node will not be easy. All of the problems with processes at 130 and 90 will be there and new ones will appear. The 65 nm node will have more and newer chemistries and much more aggressive RET (reticle enhancement technologies) for the masks. The process and design complexity will demand greater cooperation across the fabs, EDA, manufacturing, inspection, and process simulation.

The abstraction barriers between design and manufacturing are breaking down, making the knowledge challenge a more difficult chasm. The whole process window in now present within a single die and there is no such thing as typical any more. Physical shrinks are no longer the easy way to smaller devices, so process innovation will become the key, which couples with a need for better measurements and models.

Raman was questioned about user needs. He noted that costs are increasing, for both design and for manufacturing. Companies will need very large volumes of product to justify moving to 90 nm. Designers will need to know much more about manufacturing and mask issues while learning about new tool requirements and functions. Semiconductor manufacturers, both IDMs and fabless, will need help in doing failure analysis.

Levitt, when asked about a design perspective, cited a need for integrated intelligence and knowledge into the EDA tools. Next generation designs will not be able to use margins and post processing to get acceptable results, so the design flows will have to change to become more implementation centric. For example, some "dummy" features like metal fill do not need aggressive RET, but most tools use the same effort for all features on a layer. The individual device variations do not require full statistical analysis, but will require enough knowledge of the end application to apply sufficient statistical analysis. One key obstacle is the need for greater sharing of data from the various sources. Manufacturers have withheld data as a precious piece of intellectual property, but must move towards increased data sharing in an "IDM light" data use model.

Anantha noted that DFM is happening. Three issues are driving acceptance—lithography issues are becoming well defined, CMP (chemical-mechanical polishing) rules and polish friendly designs are emerging that include inspection and design aware dummy features, and OPC (optical proximity corrections) have had enough time to show results and develop accurate models.

Kibarian talked about yields and defect trends. Defect densities are increasing at the smaller process nodes, but the defects are not increasingly random. The industry is moving from post processing to rules—where the penalties and trade-offs are not quantized, to DFM models that show probabilities of cell failure and yield along with performance and power modeling. The industry is entering a new phase of circuit design where the discrete nature of atomic-level characteristics have to be addressed. In addition, all designs will eventually need to have the ability to self-repair through redundant circuitry to achieve acceptable yields.

Healy addressed the need for increased and improved testing. He noted that manufacturing is usually defined too narrowly as only involving the physical wafer processes and not including the back end, testing and packaging. The newest processes have failure modes that are not covered by stuck-at and open or shorted signals. Now the devices need at-speed testing that has fault coverage of over 99 percent to ensure good products. The ATE (automatic test equipment) with data compression is not able to achieve anything near 99 percent fault coverage and offer assistance in problem diagnostics.

Jones summarized the issues by noting that problems in manufacturing are growing and getting more severe. Increasingly the issue is data management and sharing, but the tools are not readily available, especially for the fabless companies. Sometimes the advanced technologies are not necessary and their use depends on the end application and competitive factors.

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