Stanford University, CA August 15, 2005

The 17th annual hot chips symposium on high-performance chips had William Holt, vice-president and general manager of the technology and manufacturing group at Intel Corp. (Santa Clara, CA) give a keynote presentation titled “ Facing the hot chip challenge (again)”. While Holt included the requisite Moore's Law graphs, he approached these trends from an economic and power perspective.

The original formulation of Moore's Law strongly suggested that cost was the main driver. The economics are a function of the cost of transistors per chip, since scaling devices reduces the cost per transistor by a factor of four, then there's no increase in cost for increase in device capacity or functionality. For any design, the transistor budget is a function of the area available and the processes in place to manufacture those parts. At the same time that the device geometries are shrinking, the wafer sizes are increasing; the result is that the costs per centimeter squared remaining relatively constant. This growth in wafer dimensions more than offsets the increased costs of the more complex processes.

Power challenges, however, are neither new nor fundamental. Gordon Moore asked the question in 1965 “will it be possible to remove the heat generated by tens of thousands of components?” In addition to device scaling, silicon technology has changed to increase power efficiency, one from bipolar, to PMOS and NMOS, and by the mid-1980s to CMOS. In the '90s, manufacturers started aggressively scaling voltage to hold power consumption relatively constant.

To address power efficiency, the industry is changing technologies so scaling includes both voltage and gate length. The next area for attention will be power efficient scaling to get more functions per physical resource—area and power. Future designs will require innovations in many areas to address the power issues, has the costs in resources of area and power become a constant rather than a variable in the design.

Process and design will have to work more closely together to achieve satisfactory results. Process design changes will still scale power by adjusting the variables of voltage, size, and frequency, but voltage scaling makes design considerably more difficult. High complexity solutions to power such as substrate voltage variations to change threshold voltages and therefore change leakage require extremely complex circuit designs. Even more importantly, these process migrations will not scale below 65 nanometers.

Because of the aggressive voltage scaling to reduce power, leakage has now become one of the primary sources of power consumption. Transistor performance must now be designed to either improve speed or decreased power. Process designers no longer have the luxury of ignoring power leakage in their work. Due to physical constraints, power density is now leveling off and must be managed by a combination of process and design.

Transistor technology will continue to advance. The ITRS semiconductor roadmap predicts that feature size scaling doesn't address the question of what is the most cost-effective change possible. The next-generation of processes below 65 nanometers will need to be optimized for and applications and not just for speed.

As examples of technology innovations, stray into silicon is one of many innovations that increased transistor drive strength, which equates to increased speed, without a corresponding increase in leakage. This new process modification allows the manufacture to trade off leakage and drive strength and provides results that are a function of a combined process and transistor design.

Another process change is the incorporation of high K dielectric materials to reduce leakage. The industry has gone to a point where we can no longer scale gate oxides. Therefore, processes must change materials for gate oxides to high K dielectrics. The challenge will be integrating additional materials into the process. so that structures and materials will provide the ability to continue scaling devices. Transistors will be optimized for the application.

Interconnect is still a big challenge, as a power consumer and as a structural component. In some designs, the RC delay on long paths exceeds the duration of the clock cycle. To solve this problem, future designs and processes will move towards more three-dimensional structures. This may include the addition of active layers above the substrate or other technologies such as stacked wafers and stacked die. In all these cases the interconnections between functions is greatly reduced. In addition, further work will be done on optimizing interconnect to vary metal pitch for functions based on product and process requirements.

Efficient designs will include many power reduction techniques. In conjunction with process, leakage control will come from multiple thresholds and active substrate control. Other improvements in leakage will come from new process developments. Active power reduction will come through increased use of memory, multi-threading, dual-core and multi-core microprocessors and much more special purpose hardware that can be turned off completely when not in use.

The circuit design techniques for reducing or controlling gate leakage impact the architectures and other parts of the design. Designing with multiple voltage islands and active substrate biasing controls is a complex task. Changing to extremely wide internal data words allows the same throughput at much lower clock rates, linearly reducing power consumption with clock speed. The advent of dual-core microprocessors is one example of this trend and also illustrates the software issues involved.

Therefore, process, design, and functionality will all be optimized simultaneously for a given application. On the process front new materials and new combinations of materials will become prevalent. New design approaches will allow progression and optimization of circuits by function to enable substantial performance improvements without increases in power consumption. Process and design collaboration is critical as future designs change the design space from increased circuit density to system-optimized functionality.

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