San Francisco â€“ February 6, 2006. Tze-Chiang Chen, vice president of science and technology at IBM Corp. presented a talk on "Where is CMOS going: trendy hype versus real technology" here at the International Solid State Circuits Conference.
Chen noted that many pundits are claiming Moore's law is dead and newer technologies must replace it. The ability to scale semiconductor processes is running into severe limits that prevent much more progress. Alternatives getting attention include nano-technology, bio-electronics, and bio-sensors.
Admittedly, there is progress in these areas, but not for large-scale electronics. Nano-technology is working on single memory bits with large memory arrays 5-10 years out. Individual circuits in nano-tubes are now working, but there is no reproducible way to interconnect the functions and the approach is probably 10-15 years away from production.
IBM has some roadmaps for their silicon that increases integration higher into the system level. They think that silicon CMOS is viable for at least 10 years down to around 22 nm range, since all previous "insurmountable" problems have been solved by the time the process had to go into production. An alternative is to integrate subsystems and create 3D assemblies of chips, moving towards greater parallelism, and possibly using optical interconnect for some internal layers.
Longer term, other materials and technologies will be investigated. These areas of research should show working devices in the next 10 years, with an additional 5 years needed for implementation. In addition, quantum computing offers a power reduction of 6 orders of magnitude compared to CMOS, but scaling the technology up beyond the current 6 qbits will take a lot of work.
The challenges facing CMOS are not limited to image scaling. Researchers need to find ways to reduce defect densities even more than currently possible. The issues of power consumption and thermal density now compete with SRAM stability, analog functionality, device variability and reliability, and useful methodologies to manage all the technical and design issues arising at 65 nm and smaller geometries.
All the latest challenges are a function of the process. Process variability and device leakage demand innovative power management schemes. Leakage management will require new structures and materials in the semiconductors. The innovations in devices and materials will require significant changes in design tools and methodologies.
Power design requires the capability to view real-time thermal images, since junction temperatures greater than 70°C lead to degraded performance, reduced reliability, and thermal runaway. Higher temperatures also impose constraints on packages and higher-level assemblies. Any amount of heat is allowable, but at considerable cost. A heatsink may only cost $10 but would allow a 100 W part to exceed 100°C. A heatsink with a fan could cost $30, but would limit the temperature rise to 50°C. Liquid cooling might add $50 to the assembly cost but keep the operating temperature rise at less than 20°C.
In past talks, others have noted that CMOS scaling must keep power density constant. However, these calculations are based on much greater gate oxide thickness. Now gate oxides are 1-2 layers of atoms thick and atoms don't scale. This physical challenge changes delay versus oxide thickness projections and device operating points. The thin oxides are a key contributor to the leakage and its attendant power consumption.
To solve the oxide issue, the next generations of CMOS will change to metal gate and high k dielectric materials. The high k oxides will still call for lower supply voltages, moving towards 0.3 V. At these ultra low supply voltages, delays will increase by 30x but power consumption will decrease by 300x, a reasonable trade-off. The issues for ultra low supplies are circuit functionality and SRAM stability within the framework of acceptable performance.
The change to 3D assemblies can improve system-level performance. Bonded SOI wafers can have over 106 connections per mm2 and the reduced distances resulting from vertical versus horizontal connections improves bandwidth.
Yield variability is addressed in three categories: lot-lot, regional systematic, and local systematic. All of these issues are solvable problems. The real challenge is the local random variations. Because of the atomic scale of the devices, all effects are a function of small number statistics. A few atoms change in dopant atoms or implant dose can cause a 100 mV change in threshold voltages in adjacent transistors. Line edge roughness accounts for as much as 25 percent in imaged gate length, affecting performance and power consumption. At the lower voltages, noise becomes a greater issue, especially in SRAMs.
To reduce the variability requires a change in basic device structure or a move to gridded layouts. In addition, dynamic Vdd and post-processing supply control or greater circuit redundancy will become necessary. For example, an I/O receiver is designed for an intrinsic 20 GHz bandwidth. With the mismatches due to device variability and degradations due to noise, the effective bandwidth is 6-8 GHz.
Gridded layouts and restricted design rules can help. Future designs will have a metric of yielded chips per wafer at an acceptable cost. By placing narrow features on a uniform and coarse grid, as well as keeping all narrow features in a single orientation helps yield. In addition, limiting the number of line pitches and line widths available, since some combinations of line width and pitch are not printable, makes layouts more manufacturable.
Materials innovations will enhance performance. Next generation semiconductors will use about half of the elements in the periodic table of elements, compared to the half dozen used now. Mobility enhancements will be based on the silicon crystal orientation and differential stress modifications. The interconnect will be in very low K dielectric materials eventually dropping to a range near 2.0-2.3 nm. In the long-term future, some circuits will have air gaps.
Innovation in design and technology will enable greater optimizations. The design issues will include localized power management and device variability assessment and control in the next generations of chips. CMOS is likely to be the primary technology for electronics for at least the next 10 years.