Comparing the indispensable role that EDA tools play in the semiconductor industry with the percentage of revenues EDA vendors derive from that market clearly indicates that the results are not commensurate with the contributions. The EDA industry came into existence and has been managed ever since as a service industry that offers an alternative to in-house developed computer-based tools for the design of electronic circuits. Therefore its pricing structure is founded on the replacement value of an activity on the cost side of the ledger, not on the much more attractive profit side. One of the hardest obstacles to overcome for EDA companies wanting to change this approach is the difficulty of demonstrating the clear and measurable contribution they make to the development and manufacture of an integrated circuit (IC) so that they can be rewarded with part of the profits from the sale of the IC, not from the increase of the designers productivity. Obviously when a company is purchasing tools for their engineers, it tries to minimize costs as well as maximize productivity. The resulting market is very competitive, prone to discounts in order to win the order, and seldom results in establishing true partnerships between the EDA vendor and its customers. EDA companies are forced to set a price that is low enough to keep competitors out of the account, yet high enough to generate some profit. Unfortunately this is not a recipe for a healthy and growing industry. The only factor that has kept the EDA industry on a growth pattern is the significant amount of money invested by venture capital in new EDA companies responsible for most of the new technology that has kept the industry viable.

Both EDA vendors and customers have talked about Register Transfer Level (RTL) signoff for years, but there has been very little action toward making it a reality. In part this is justified by the desire of engineers to maintain control of all details of the creation of their ASIC designs. In part it is due to the lack of a real economic motive to adopt this particular mechanism to pass a design from a system company to a semiconductor one. In fact from an economic point of view EDA vendors have an imperative to make sure that RTL signoff never comes to pass. Tools that handle the design after the RTL netlist is developed generate most of the EDA revenues. Tools like synthesis (both logical and physical), place and route, and, most recently, the ensemble of analysis and corrective tools that belong to the Design for Manufacturing (DFM) and Design for Yield (DFY) design flow. Dataquest 2004 EDA Market Forecast shows that in 2003 tools used to work on the design after the RTL netlist generated about $1.3 billion in sales while tools used to generate the same netlist generated $465 million in revenue.

The post RTL tools demand the highest yearly license price while EDA tools used to generate the RTL representation have significantly lower unit license prices. The ESL segment, in spite of significant marketing efforts, is still a small portion of the market, although the mixed languages simulation and verification sector is growing. Thus between the need of engineers to adjust the very last detail of a chip layout and the need of EDA companies to keep their established revenues stream, why have we not just drunk the Kool-Aid and forgotten about the RTL signoff chimera?

The reason is simple: both engineers and EDA companies need it, now more than ever, as we are approaching the use of Very Deep Sub-Micron (VDSM) processes, those with feature sizes at 65 nm or smaller.

In order to produce a VDSM layout that has acceptable yields, engineers require such an intimate knowledge of process chemistry and physics, of optics and reticle construction, even of fab test equipment, to make it practically impossible for a design team to achieve the goal. In fact, only a design team with full access to the fab and the ability of both the design house and the semiconductor vendor to modify their portion of the flow to produce a fully integrated development and fabrication environment can insure success. Designers can no longer just release a GDSII file to the fab, just like the fab cannot specify a set of design rules that apply to all designs. Even at 90 nm IDM companies that own both the design and the fabrication portion of the problem are showing significant better results than companies that must rely on a foundry for the manufacturing process. Today every design steps from synthesis to GDSII is part of the manufacturing flow. It is better if one entity, namely the semiconductor company, owns the entire manufacturing process.

In order to fully enable RTL handoff, the industry must improve the front-end design process. Designers must address the issue of testability at the system level, while they are developing the architecture of the system instead of inserting test structures after the circuit has been synthesized. This process may require modifications to the synthesis tools, but I predict that the modifications will not be very expensive to implement. Signal integrity and power analysis are two other issues that require attention during both the architectural phase and the RTL netlist development phase. Tools that address both issues now rely mostly on analysis of extracted parameters using gate level netlists. Both areas require tools development as well as engineers training. The additional tools and an increase in sophistication of architectural tools, hardware/software co-development, and production of HDL circuit description, what some people call behavioral synthesis, and much more powerful formal verification tools will increase the market size of front-end EDA tools.

I have based all my projection on the previously mentioned Dataquest 2004 Market Forecast. The report shows that by combining the projected revenues of ESL, simulation and verification, and formal verification segments, EDA revenues for 2006 will be slightly over $1 billion and grow to over $1.25 billion in 2007. Revenues for all tools that now support development from logic synthesis to tapeout are projected to total $1.7 billion in 2006 and almost $2 billion in 2007. For those keeping score let me quickly point out that the remaining revenues necessary to make up the total yearly market size also include PCB design revenues as well as other IC related revenues that will not be materially impacted by the introduction of RTL signoff. Non-the-less loosing between 40 and 50% of revenues is not a prospect any industry cherishes.

The solution is for EDA companies to partner with the semiconductor companies, both foundries and IDMs, and revisit the licensing model. Of course in practice this approach is only achievable by the largest four companies, Cadence, Magma, Mentor, and Synopsys, who already have well-established relationships with semiconductor manufacturers. The reason for this approach is that it is more difficult to calculate the contribution to revenues of say an MP3 player from the IC contained in the product developed with certain EDA tools in order to obtain royalties from the system house. Calculating royalties when the semiconductor vendor sells the IC is a more straightforward approach.

Instead of following the financial model that values an EDA tool based on its replacement value if it had been developed in-house, the new model would consider the EDA vendor as a partner in the manufacturing process. As such an EDA vendor would receive a royalty payment based on the number of parts sold for each design. Since in 2004 the total revenues of the semiconductor industry was approximately $308 billion, even a modest 1% royalty would generate more income for the EDA sector than what it will loose as a result of the adoption of the RTL signoff model. With the present pricing structure EDA sales are related to the number of new design starts, while using the new model only the pre RTL netlist tools will continue this approach while the rest of the IC design tools revenues would be based on the size of the end market.
The result is a new EDA landscape that clearly delineates those products that serve the front-end design and those that support the manufacturing of integrated circuits. The two classes of products can have different pricing schemes. The fact that it will still be difficult to quantify the contribution of an ESL product to the manufacturability of an IC will not impact the pricing structure for a physical synthesis tool, for example.

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