I do not think it is an accident that Synopsys chose to introduce its new EV6x processor solutions the week before the Embedded Vision Summit that will take place at the Santa Clara Convention Center the week of May 21.
The ASIL B, C, D Ready DesignWare EV6x Embedded Vision Processors with Safety Enhancement Package integrate safety-critical hardware features while maintaining high performance and minimizing area and power.
The development of the IP has taken advantage of another Synopsys product ASIP Designer that is pertinent to what will go on at the Embedded Vision Summit. By the way for those not familiar with all the four-letter words in electronics ASIP stands for Application Specific Instructions set Processor.
ASIP Designer allows you to build your own processor with far less uncertainty and expenditure than if you had to do it on your own.
The EV6x Processors with SEP include differentiated hardware safety features, safety monitors, and lockstep capabilities for safety-critical designs. These features enable designers to achieve the ISO 26262 standard’s most stringent level of functional safety and fault coverage without significant impact on performance, power, or area compared to the non-ASIL Ready EV6x processors. The ASIL Ready EV6x Processors with SEP integrate scalar, vector DSP, and convolutional neural network (CNN) processing units to help speed certification of automotive systems that require deep learning functionality.
ASIL D Ready ARC MetaWare EV Development Toolkit for Safety provides a complete set of tools and runtime libraries to speed software development for AI applications. The associated comprehensive safety documentation, including FMEDA reports and safety manuals, accelerates SoC-level functional safety assessments.
The Embedded Vision Summit offers to its attendees that opportunity to hear presentations about technologies employed in Embedded vision systems, meet exhibitors, and network with over a thousand of attendees over the four days of the event.