February 2, 2006â€”Palo Alto, CAâ€”EDAC held its annual CEO forecast panel at HP's headquarters building. Don Clark of the Wall Street Journal moderated the panel. The panel members were: John Bourgoin - MIPS Technologies, Aart de Geus â€“ Synopsys, Michael Fister â€“ Cadence Design Systems, John Kibarian â€“ PDF Solutions, Gary Meyers â€“ Synplicity, and Wally Rhines â€“ Mentor Graphics. Clark opened with the statement that the Wall Street Journal mostly neglects EDA companies and its markets.
Each panelist made a short position statement. Bourgoin indicated the drivers for the IP portion of the market are increasing IP reuse, stable interface and transaction standards, and the displacement of ASICs by programmable logic devices. The growth drivers are consumer products such as TVs and wireless systems. The accompanying challenges are the need for hardware and software verification in systems functions, leading to greater use of ESL and platform-based designs. Because the actual design cycles are almost 3 years long, the recent increases in licenses implies a robust growth in a few years as the larger royalty streams materialize.
Aart de Geus agreed that the drivers are mostly consumer functions, but noted that infrastructure capabilities have to improve while total costs of broadband use have to decrease. The next generation of products will need both technology and business model breakthroughs to benefit from the vast increases in complexity available from the next generation semiconductor processes.
Fister described a need to change focus to more closely link the costs of development with the increases in productivity necessary to provide the means for economic viability. In addition, he suggested that products must be segmented by value proposition, since not everyone needs the power user set of tools and capabilities. He proposed a shift to a correct-by-construction methodology to replace the "fix it again" mode in current use. He noted that Cadence has seen 11 percent year to year growth during his tenure.
Kibarian demurred from making any forecasts, since his domain is the detailed manufacturing knowledge base. He did disclose that overall steady-state yields are dropping with each new process node. The silicon engineering offers the tradeoff of performance and variability, but the DFM knowledge base needs to move to the design area to be useful. Future design criteria will include some metrics on expected good die per wafer, so increased circuit redundancy will be necessary.
Meyers asserted that increasing development costs are leading to a lower number of design starts. The performance capabilities of the various processes are opening a window for programmable devices. The typical ASIC is in 130 nm or larger processes while the FPGAs are expected to be in 65 nm this year. The difference in capacity and performance is becoming irrelevant, so the design and NRE costs are the determining factor in logic fabric choices. The emergence of tools for software engineers that produce programmable logic bit streams will increase the overall design market by as much as an order of magnitude. Meyers then became to first CEO to give an EDA forecast at the panel: about 7 percent growth for 2006 over 2005.
Rhines performed some economic legerdemain to show that the EDA industry, with its now common 3-year licenses, depends upon the first derivative of the semiconductor R&D budgets. In other words, if the semiconductor R&D budgets are continuing to grow at the time of license renewals, EDA grows. If they are falling, EDA revenues follow after some lag time. From this analysis, Rhines predicts 2006 to be up about 2.3 percent and up 5.8 percent in 2007.