East West Center, Honolulu, Hawaii, USA

published in International Journal of Innovation Management, special issue in honour of Keith Pavitt , Vol.9, No.1, March 2005

(Posted with the Author’s Permission)

ACKNOWLEDGEMENTS

This paper draws on discussions with Keith Pavitt, as part of an email correspondence during fall 2002. I am grateful for comments from the editors and reviewers, and from Grant Martin, Barry Naughton, Ove Granstrand, Bruce Kogut, Hiroyuki Chuma, Shen Xiaobai, Norio Tokumaru, Kazufumi Tanaka, Boy Luethje, Stefano Brusoni, David Levy, Shin-Horng Chen, AnnoLee Saxenian.

Introduction

Among Keith Pavitt’s many contributions to the study of innovation is the proposition that physical proximity is advantageous for innovative activities that involve highly complex technological knowledge (Pavitt, 1999: XI). Cognitive and organizational complexity explain why innovation is an “important case of ‘non-globalisation’”(Patel and Pavitt, 1991).

Following this argument, one would expect a highly complex innovative activity like chip design -- a process that creates the greatest value in the electronics industry -- to be spatially immobile, much less prone than manufacturing to geographic relocation. Until quite recently, chip design has indeed remained heavily concentrated in a few centers of excellence, mainly in the US, but also in Europe and Japan. However, fundamental changes have occurred over the last few years in the location of chip design that are signaling a growing geographical mobility. Of particular importance has been a massive dispersion of chip design to leading Asian electronics exporting countries.

The paper explores why chip design is moving to Asia, despite its extraordinary complexity. It shows that Pavitt’s framework can shed new light on the link between complexity and internationalization of innovation. To establish what is really happening, I interviewed 60 companies and 15 research institutions in the US, Taiwan, Korea, China and Malaysia that are involved in electronic design (for integrated circuits as well as systems). In the interviews, I distinguished “pull”, “policy” and “push” factors to examine what forces are behind the growing geographic mobility of chip design, and its dispersion to Asia.

“Pull” factors are demand-oriented and supply-oriented forces that attract chip design to particular locations. “Policy” factors are policies and regulations in both home and host countries that affect differences in the cost of conducting innovation across locations. Both factors are roughly identical with the “centrifugal” forces for geographical decentralization that have been identified by research on the internationalization of innovation. I argue that, while “pull” and “policy” forces are important, they may not be sufficient to explain what tilts the balance in favor of decentralization. To reduce this gap in our knowledge, I examine “push” factors, i.e. changes in design methodology (“system-on-chip design”, or SoC) and organization (“vertical specialization” within global design networks, or GDNs), and explore the pressures and opportunities that these changes provide for the internationalization of design. Vertical specialization within GDNs implies that stages of chip design are outsourced to specialized suppliers (disintegration of design value chain) and relocated across national boundaries (geographic dispersion). The resultant increase in knowledge mobility explains why chip design that, in Pavitt’s framework is not supposed to move, is moving from the traditional centers to a few new specialized design clusters in Asia.

Part 1 introduces the conceptual framework that underlies the distinction between pull, policy and push factors. Part 2 reviews findings of interviews with main carriers of chip design in Asia that demonstrate substantial progress in the complexity of relocated design stages and capabilities. Part 3 examines the role played by “pull” and “political” factors. “Push” factors are addressed in the rest of the paper. In part 4, I explore how changes in design methodology and organization have pushed vertical specialization within GDNs deeper into the design value chain. Finally, part 5 documents pressures and opportunities that vertical specialization is creating for GDN participants to move chip design to Asia.

1. Conceptual Framework

The question how globalization affects the geographic dispersion of knowledge and innovation, and whether this fosters or constrains local capability formation has played an important role for theoretical debates on the role of foreign direct investment (FDI) and multinational corporations (e.g., Dunning, 1998). More recently, this question has also received attention in innovation theory and economic geography.

The dominant position has been that innovation, in contrast to most other stages of the value chain, is highly immobile: it remains tied to specific locations, despite a rapid geographic dispersion of markets, finance and production (e.g., Archibugi and Michie, 1995). In a widely quoted article, Patel and Pavitt (1991) use patent data to demonstrate that innovative activities of the world’s largest firms are among the least internationalized of their functions. Attempts to explain such spatial stickiness of innovation have focused on the dynamics of spatial agglomeration, arguing that clustering effects are particularly important for knowledge externalities and spillovers (e.g., Feldman, 1999; Porter and Sølvell, 1998; Jaffe et al, 2000). The main reason for such spatial stickiness is the inter-active nature of innovation (Kline and Rosenberg 1986): it requires dense knowledge exchange (much of it tacit) between users and producers within localized clusters.

Pavitt’s focus on the dual challenges of cognitive and organizational complexity adds greater precision to this literature. Let us apply these concepts to chip design. “Cognitive” complexity means that a chip is “made up of numerous components and subsystems whose interactions are often non-linear and therefore impossible to predict” (Pavitt, 1999: p.X). Verification and testing thus become critical bottlenecks for controlling the performance of a chip. Specialized software tools for design automation are available to codify some elements of this knowledge. Yet, this cannot substitute for dense exchange of (mostly tacit) knowledge among co-located design communities, which is necessary for “knowing how and where to search for improved performance” (ibid). And “organizational” complexity implies that “a wide and increasing range of fields of specialized knowledge” need to be mobilized to take a specific chip from its initial design to its widespread use, which necessitates “linkages with the wider knowledge communities and the capacity within the firm to experiment and learn across cognitive and functional boundaries” (Pavitt, 1999: pages X and XI).

Pavitt argues that, to cope with such demanding requirements, firms have a strong incentive to concentrate innovation in their home country. That national bias “reflects the linguistic and geographic constraints imposed by person-embodied exchanges and transfers of tacit knowledge.” (Patel and Pavitt, 2000: 218). However, research on globalization has clearly established that the center of gravity has shifted beyond the national economy. International linkages proliferate, as markets for capital, goods, services, knowledge and labor are integrated across borders. While integration is far from perfect in markets for technology (Arora et al, 2001), it is nevertheless transforming the geography of innovation (Ernst, 2002a). This process is well captured in Cantwell’s important observation that, instead of a few pre-eminent centers of innovation, there are now “multiple locations for innovation, and even lower-order or less developed centers can still be sources of innovation.” (Cantwell, 1995: 172).

What forces explain the internationalization of innovation despite the proximity constraints imposed by knowledge complexity? Research on the internationalization of innovation typically explores “pull” factors, i.e. demand-oriented and supply-oriented forces that attract R&D to particular locations (Granstrand et al, 1993; Cantwell and Iammarino, 2003). A key proposition is that the “centrifugal” forces for geographical decentralization can be stronger than the “centripetal” forces for geographical centralization when the host country market is large, and displays rapid growth and increasing sophistication. In high-tech industries like electronics, supply-oriented forces are even more important (Dalton et al. 1999: 40; Ernst, 1997). This includes proximity to global manufacturing bases, but also the search for lower-cost overseas R&D personnel and for new ideas and innovative capabilities. “Policy” factors that affect differences in the cost of conducting innovation across locations, have been identified as additional powerful drivers for the internationalization of innovation (e.g., Callan et al, 1997). Their role has been acknowledge in Patel and Pavitt (1991: 18):” …we expect to see greater internationalization of large firms’ technological activities in the future, not because it is inherently more efficient, but because it is politically necessary.”

This pretty much sounds like a final statement. However, one of Pavitt’s great strengths is that he did not believe that theories are made for eternity. In a review of future directions of research, he emphasizes that “new theories emerge from new data” (Pavitt, 1999: XVII). This paper demonstrates that, on internationalization of innovation, we have accumulated a critical mass of new data to ask new questions and to construct new theories. For instance, new research on learning strategies and innovation systems in latecomer societies has added greater precision to the analysis of both “pull” and “policy” factors that attract innovation to particular locations (e.g., Hobday, 1995; Kim Linsu, 1997; Lall, 2000; Ernst, Ganiatsos and Mytelka, 1998).

But to get to the root causes that shift the balance in favor of geographical decentralization, we need to examine new data on “push” factors, i.e. changes in the methodology and organization of innovation. For instance, we now know that the fast pace of innovation and its disruptive nature keeps changing rapidly firm strategies and industry organization (e.g., Christensen, 1997), giving rise to more “open innovation systems” (Chesbrough, 2003). However, we are only just beginning to explore what this implies for the spatial mobility of innovation.

I use the example of chip design to demonstrate that Pavitt’s conceptualization of cognitive and organizational complexity can help us to analyze this important issue. A central proposition of the paper is that chip design is moving to Asia in response to radical changes in design methodology (SoC design). These changes that were introduced to improve design productivity, instead have further increased the cognitive and organizational complexity of design. As a result, integrated forms of design organization, where (almost) entire ICs are designed within a single firm, are giving way to vertical specialization within global design networks (GDNs), where stages of chip design are outsourced to specialized suppliers (disintegration of design value chain) and relocated across national boundaries (geographic dispersion)[1]. I show in part 4 that vertical specialization increases the number and variety of GDN participants, business models, and design interfaces, bringing together design teams from companies that drastically differ in size, market power, location and nationality.

This poses very demanding challenges for knowledge-sharing. Hence, the main purpose of GDNs is to facilitate the exchange of diverse specialized bodies of knowledge between geographically dispersed communities of engineers that are all contributing to a particular chip design project. Dispersion however coexists with agglomeration - the relocation of chip design is concentrated on a handful of new specialized overseas clusters, primarily in Asia. To understand why, we need to address a second question: What makes it possible to exchange complex knowledge even if innovation agents are located at distant locations?

New findings of research on the geography of innovation and economic clustering provide a key for answering this question. Breschi and Lissoni (2001) for instance emphasize that intrinsic features of knowledge do not automatically determine whether innovation is spatially concentrated or dispersed. Instead, the location of innovation is shaped by the complex interplay of the economics of knowledge diffusion, the market for knowledge workers, and the innovators’ strategies to protect and exploit its intellectual property rights. The example of chip design confirms the importance of all three factors.

Of particular importance for our purposes however is that we distinguish between “geographic” and “cognitive” proximity. Members of a specialized knowledge (‘epistemic’) community share rules and codes of exchanging knowledge. Such communities “may well survive the end of co-localization of their members.” (Breschi and Lissoni, 2001: 991). Even when dispersed far away in space, members of such communities “will share more jargon and trust among each other than with any outsider within their present local communities. And even when meetings are required, their frequency will not necessarily be as high as to impose co-localization as a necessary requirement for belonging to the epistemic community.” (ibid.). In short, for innovative activities that require complex knowledge, it is possible to reproduce cognitive proximity affects even if design communities are located at distant locations, such as Silicon Valley, Taiwan’s Hsinchuh Science Park, Beijing, Shanghai and Seoul.

2. Chip Design in Asia

A massive relocation of electronics design is under way to (non-Japan) Asia. This region is the fastest growing market for EDA (= electronic design automation) tools, growing 36% in the first quarter of 2004, compared with 5% growth in North America, 4 % in Europe, and -2 % in Japan (EDA Consortium, 2004). Asia’s share in the global production of chip designs has increased from practically nothing during the mid 1990s to around 30% in 2002, relative to North America’s share of 60% (iSuppli, 2003: 21). Until 2008, Asia’s share is projected to grow to more than 50%. Such projections are in line with a widespread consensus in the interviews, that the center of gravity of the global semiconductor industry is rapidly shifting to Asia, with chip design following fabrication (“foundries”) and the emergence of large Asian system companies (as customers and captive developers of chip designs). Taiwan has emerged as a primary new location, with Korea following closely behind, and chip design is rapidly growing in China and India, as well as in Singapore and Malaysia[2].

2.1. Carriers

To move beyond such broad-brush figures, I conducted exploratory, semi-structured interviews during 2002 and 2003 with a sample of 60 companies and 15 research institutions in the US, Taiwan, Korea, China and Malaysia that are involved in electronic design (for integrated circuits as well as systems). The sample contains some of the main global and regional carriers of chip design in Asia. It includes specialized research institutes as well as nine strategic groups of firms that participate in global design networks (GDNs)[3]: system companies; integrated device manufacturers (IDMs); providers of electronic manufacturing services (EMSs) and design services (the so-called ODMs, or “original-design-manufacturers); “fabless” chip design houses; “chipless” licensors of “silicon intellectual properties” (SIPs); chip contract manufacturers (“foundries”); vendors of electronic design automation (EDA) tools; chip packaging and testing companies; and design implementation service providers. Over the last few years, all interviewed firms have made substantial investments in chip design-related activities in Asia, and they are planning to expand such activities[4].

2.2. Complexity - stages and capabilities

Two questions in the interviews address the issue of complexity. Drawing on a flow chart for chip design (Figure 1), the first question asks firms to disaggregate their design activities into routine functions (“design implementation”, i.e. the six boxes in the middle of the figure that are un-shaded) and stages of design that center on conceptualization (“system/application specification“, i.e. the three shaded boxes in the upper part of the figure).

Figure 1: Taiwan’s Competitive Advantage in Digital Circuit Design Source: Chang and Tsai, 2002

The interviews show that design implementation continues to play a dominant role, but that system specification is gaining in importance. Design implementation remains the defining characteristic for providers of design services (ODMs), as well as (more recently) for providers of electronic manufacturing services (EMSs). This reflects a long experience in board-level design that goes back to the early 1980s (Ernst and O’Connor, 1992), but today it covers very complex multi-layer boards. Combined with the experience in detailed product design and engineering that Asian firms have accumulated in the fabrication of ICs, board-level design has given rise to a broad portfolio of design implementation capabilities. Design implementation also remains an important strategic focus of Taiwanese design houses. In line with earlier research by Chang and Tsai (2002), the interviews highlight competitive strengths of these firms in the speed, cost, flexibility and quality of providing design implementation services.

Interview responses also show considerable progress in system specification. There are strong incentives - a capacity to specify systems and applications provides leverage for defining global standards and for innovation rents via premium pricing. One approach, chosen primarily by Taiwanese design houses, are niche strategies as suppliers of SIPs. However, the main Asian carriers of system specification are leading system companies (especially from China, Korea, and Taiwan) that are producing innovations in the design of complex system architectures[5], primarily for wireless telecommunication systems. Finally, global system companies and IDMs report that their rapidly expanding design centers in Asia perform both design implementation and system specification (mainly for Asian markets). This reflects the diversity of functions that these centers perform in GDNs.

In the second question, firms are asked to establish the complexity of their design activities, by using standard industry metrics. such as the line-width of process technology (measured in nanometers); the use of analog and mixed-signal design (that are substantially more complex than digital design); the share and type of system-level design (e.g., system-on-chip, system-in package, structured ASICs); and the number of gates used in these designs. I have added the second question, because system specification does not always require more complex knowledge than design implementation. Knowledge complexity depends on how much functionality is squeezed onto the chip, the printed circuit board, or the system. Equally important is the sophistication of the design methodology. Knowledge complexity tends to increase substantially for the six design implementation stages, the closer chip design is moving from the individual component to system-level integration, and the greater use is made of “modular design”.

The interviews show that a few leading Asian firms in the sample perform highly complex design activities across all of the above complexity indicators. This is the case primarily for system companies, integrated device manufacturers (IDMs), foundry service providers and a few design houses. By nationality, design complexity is highest for Korean and Taiwanese firms. Design complexity is also high for Chinese telecommunications equipment vendors[6]. The rest of the Asian sample firms however are situating themselves “at least one generation behind” the leading-edge in design complexity as fast, but cheaper followers. Finally, the Asian design centers of global firms report a wide range of design complexity levels, again reflecting the diverse functions of these centers.

3. Pull and Policy Factors

As expected, global firms are attracted by supply-oriented forces, especially the lower cost of employing a chip design engineer in Asia, which is typically between 10 and 20% of the cost in Silicon Valley (Figure 2).

Figure 2

However, demand-oriented factors are equally important. Global firms emphasize the need to relocate design to be close to the rapidly growing and increasingly sophisticated Asian markets for communications, computing and digital consumer equipment, to be able to interact with Asia’s lead users of novel or enhanced products or services. The main prize is the sheer size of China’s market for IT hardware and services. China is the world’s largest market for telecommunications equipment (wired and wireless), as well as a test bed for 3G and next generation wireless communication systems. China is also one of the most demanding markets for computing and digital consumer equipment. As most of that equipment is produced in China, the country has become the world’s third largest market for semiconductors, generating substantial demand for chip design.

To penetrate Asia’s growth markets, global IDMs and system companies attempt to expand their “platform leadership” strategies across the region[7]. For mobile communication systems for instance, all major global system companies are expanding their Asian chip design centers to establish their own “platform” designs as de facto standards in the region. Global firms consistently emphasize the diversity of functions that Asian design centers are playing in their GDNs. This includes routine tasks (engineering support, adaptation and listening posts for ‘technology marketing’) and strategic tasks (global development mandates for specific IT products, components, and services). Which task portfolio is chosen for a particular Asian design center depends on site-specific characteristics that define the quality of the regional and national innovation systems.

Global firms emphasize that policies that provide incentives and “public goods” (especially low-cost but high-quality infrastructure) can play an important role in attracting chip design to particular locations. [8] [9] This emphasis on peculiar site advantages supports Pavitt’s proposition that “country-specific factors ….determine the volume of technological activities, and …their direction.” (Patel and Pavitt, 1991: 18). However, clustering is no longer restricted to the home location.

Asian firms acknowledge that “policy factors” played a powerful catalytic role in establishing critical infrastructure, support industries and design capabilities that enabled these firms to invest in and upgrade chip design[10]. Some Asian firms highlight peculiar features of product and factor markets that are shaped by diverse government policies and regulations. To take just one example: differences in Asian financial markets have led to diverse approaches to investment finance (e.g., debt, equity or retained earnings) that have shaped the volume and direction of investment in chip design. For instance, Taiwanese firms that rely primarily on equity report pressure to produce high margins as an important incentive to upgrade their design capabilities[11].

Finally, Asian firms emphasize that progress in chip design owes much to concerted efforts by both governments and leading companies in these countries to establish new sources of innovation and global standards. Take telecommunications, where Korea’s four leading players (Samsung, SK Telecom, KT, and LG) are all engaged in serious efforts to become major platform and contents developers for complex technology systems, especially in mobile communications. These efforts can build on considerable capabilities, accumulated in public research labs (like the Electronics and Telecommunications Research Institute, ETRI), as well as in R&D labs of the chaebol, to develop complex technology systems like TDX (a switching system) and communication systems that are based on the CDMA (= code-division multiple access) standard. Furthermore, China’s attempt to develop an alternative third generation (3G) digital wireless standard, called TD-SCDMA (time-division synchronous code-division multiple access), has created a powerful motivation to expand Asian electronic design activities for all strategic groups in our interview sample.[12]

In short, pull and policy factors explain what attracts chip design to particular locations. But they do not explain why chip design, despite its extraordinary complexity, can now be conducted at multiple locations.

4. “Push” Factors

To explain the new mobility of chip design, I examine the role of “push” factors. I first describe how changes in the methodology and organization of chip design that were introduced to improve design productivity, instead have further increased the cognitive and organizational complexity of design. I will then explore organizational responses that led to vertical specialization within GDNs and describe key features of these networks. In contrast to earlier expectations of arms-length “frictionless” contracting in chip design (Langlois, 2003; Linden and Somaya, 2003), I show that GDNs are fairly long-term arrangements that are shaped by corporate strategies[13].

4.1. System-on-Chip (SoC): design methodology and complexity

Since the mid-1990s, intensifying pressures to improve design productivity, combined with increasingly demanding performance requirements for electronic systems have produced an upheaval in chip design methodology[14]. “System-on-chip“ (SoC) design combines “modular design” [15] and design automation to move design from the individual component on a printed circuit board closer to “system-level integration” on a chip (Martin. and H. Chang, eds., 2003).

A widening productivity gap between design and fabrication has been a primary driver behind these changes in design methodology. While the productivity of semiconductor fabrication has seen a 58% compounded annual growth since the 1980s, the productivity of chip design has lagged behind, with only a 21% compounded annual rate (SIA, 1999). There is also an important time dimension to this gap, as rapid technology change shortens product-life-cycles. Manufacturing cycle times are measured in weeks, with low uncertainty. However, design and verification cycle times are measured in months or years, with high uncertainty. In the end, the design productivity gap reflects a growing mismatch between process and design technology -- the number of available transistors has grown faster than the ability to design them meaningfully (ITRS 2002: 81). Miniaturization has resulted in chips of nanometer feature size - it is now possible to fabricate millions of transistors on a single chip. The resultant increase in design complexity must be matched by a dramatic improvement in design productivity (ITRS 2004: 13,14).

A second challenge for chip design are the increasingly demanding performance requirements for electronic systems. The convergence of digital computing, communication and consumer devices has produced electronic systems that all strive to become lighter, thinner, shorter, smaller, faster and cheaper, as well as more multi-functional and less power-consuming. Essential performance features are expected to double every two years, time-to-market is critical, and product-life-cycles are rapidly shrinking to a few months. Hence, time compression is essential in designing chips for such systems - chip design cycles of months or years are no longer acceptable.

As befits such a drastic change in design methodology, the initial euphoria was soon followed by a recognition that, while a shift to system-level design based on modularization is overdue, its implementation is going to be very, very difficult[16]. In contrast to initial expectations, design complexity increased significantly. A combination of advanced process geometry (with feature size below 130 nanometers) and progress in SoC design has dramatically increased cognitive complexity at two levels of chip design: on the chip (“silicon”) and on the “system”. “Silicon complexity” refers to malfunctions that result from the growing scale and density of the circuit and the introduction of new materials or design architectures. “System complexity” on the other hand increases with the transition to system-level design with “exploding” multiple functions, like in smart phones (ITRS, 2002: 82,83). As a result, verification and testing have become a critical bottleneck, which is in line with Pavitt’s conceptualization of cognitive complexity. With growing design complexity, it becomes necessary to verify early and frequently whether the SoC design can be produced at sufficiently high yield, and whether it will do what it is expected to do. 60 to 70% of SoC hardware design time now goes into verification, leaving only 30 to 40% for the actual device development. This obviously constrains considerably the productivity of design.
Today, the debate has shifted to the limits to system integration, or what industry insiders call the “SoC crisis”. According to a vice president for design at Motorola, “ a single-chip GSM handset would require three to four years, a 300-person design team and would be sadly uncompetitive.” (EEdesign, 2003a). The overall development cost for complex 90nm chip design can be as high as $ 100 million, with most of this due to software design. After the bursting of the “New Economy” bubble, design companies and IC users can no longer afford such horrendous design costs. Design houses find it very difficult to win design-ins from global system companies who are reluctant to invest in new product development that uses unproved chip technology. For chip design, this implies that improving performance features (the main concern of system companies) needs to be combined with a relatively conservative approach to design methodology that helps to avoid low manufacturing yields[17].
However, my interviews show that Asian system companies are more willing to use new and unconventional chip designs. As attackers, they are keen to use chip designs that they believe could help them to capture market share from global industry leaders, whether through new performance features or faster speed-to-market[18]. This sets Asian system companies (e.g., Huawei or Samsung) apart from the global market leaders who are more cautious and unwilling to shoulder the higher costs and risks of innovative designs. Some interview respondents emphasize that this shift in the market for SoC designs to Asia provides a further powerful incentive for global IDMs and design houses to relocate chip design to that region.

4.2. Organizational Responses - Vertical Specialization within Global Design Networks

Until the mid-1980s, system companies and IDMs did almost all their chip design in-house. Vertical integration corresponded to a focus of design on the individual component to be inserted on a printed circuit board. Since then, SoC design has fostered vertical specialization in project execution, enabling firms to disintegrate the design value chain as well as to disperse it geographically. This gave rise to complex, multi-layered GDNs with variable configurations, depending on the needs of a specific project[19].

Figure 3 illustrates possible GDN configurations. The network core encompasses five strategic groups of firms: The “system company” defines the concept, but may well outsource everything else. SoC design may take place within the “system company”, an IDM, or a fabless (or a combination of these). And chip fabrication and assembly may be outsourced to specialized suppliers. A secondary GDN layer consists of suppliers of tools (for electronic design automation, EDA; verification; and chip testing), SIP licensors, and design implementation services. And a third layer may involve system contract manufacturers (both EMS and ODM).

Figure 3

Initially, vertical specialization has loosened the bonds between design and fabrication. This process started with ASIC design, where the goal was to avoid the very high cost and time required to design a full-custom IC[20]. An important catalyst was the establishment of Taiwan’s TSMC in 1987 as a provider of contract chip fabrication (“silicon foundry”) services for “fabless” design houses that outsource chip fabrication and target specialized niche markets. Until the early 1990s, GDNs were centered on the well-known symbiotic fabless/foundry relationship, and hence retained a relatively simple structure.

Over time however, vertical specialization has increased the number and variety of GDN participants, business models, and design interfaces, bringing together design teams from companies that drastically differ in size, market power, location and nationality. Take a SoC design network described by one interview respondent: a Chinese system company that defines the system architecture; a Taiwanese EMS that is responsible for contract manufacturing of the electronic equipment; an American IDM that provides a design platform; a European SIP provider; fabless design houses from the US and Taiwan; foundries from Taiwan, Singapore and China; chip packaging companies from Taiwan and China; tool vendors for design automation and testing from the US and India; and design support service providers from various Asian countries.

In short, vertical specialization within GDNs has fundamentally transformed the structure and the competitive dynamics of the global semiconductor industry, with new firms entering the stage as specialized suppliers. This has dramatically increased the organizational complexity of GDNs.

A good indicator is the variety of design interfaces that need to be coordinated. An interface is created when information must flow, and when knowledge must be exchanged, “…between groups that are isolated from each other, whether by goals, methodologies, geography or culture” (Wilson, 2003: 49). The diversity of functions that must be integrated into a SoC design means that “various blocks within the finished design will have come from different groups, some within and some outside the design team. Some of these groups will not be involved in the chip design process at all, and may not share a vocabulary, or even a language and culture with the primary chip design group.” (Wilson, 2003:48). A typical SoC design team needs to manage at least six main types of design interfaces: with system designers, with SIP providers, with software developers, with verification teams, with EDA tool vendors, as well as with foundry services (fabrication).

These different design communities are spread across diverse GDN participants that are rarely co-located. Coordinating these multiple design interfaces is very demanding. For instance, each of the different design network communities insists on using their own language and tools. Typically, in SoC design teams, there are “islands of automation” of different design tasks, each based on a different language. “Nobody will easily give up the language or the approach used for their own particular task for the sake of the overall flow” (EEdesign, 2002a). This poses a serious challenge to GDN organization[21]. As design teams become larger and geographically dispersed, more formal interfaces are necessary between the different network nodes. Design groups that are separated by distance or design disciplines need to be able to communicate with each other. While they share a common objective, they use highly dissimilar vocabularies. Defining interfaces requires shared definitions of the data that need to be exchanged, of the formats and protocols that govern data transfer and interpretation, and of the economic performance requirements of the designs. Developing a precise common vocabulary for these three interface attributes is extremely difficult. Equally important, data must be translated into a form usable by different design groups within GDNs.

For instance, SoC design requires close interaction with system designers, marketing people and customers ( mostly system companies). With product life cycles often as short as six months, system design requirements keep changing. The protocol necessary to transmit these changes real-time to design network participants is “one of the great unsolved problems of design management”. (Wilson, 2003: 56). Communication problems are particularly serious between hardware and software designers. Hence, proximity and face-to-face contact are important. As we have seen, Asia not only provides important growth markets for existing electronic products and services, but also test beds and launch markets for innovations and global standards in mobile communications and digital consumer electronics. Interview respondents indicate that GDNs need to locate those chip design stages in Asia that strongly interface with Asia-based system companies.

But design interface management also requires a reversal of the earlier decoupling from fabrication. Decoupling was based on well documented and automatically checkable “design rules” (Macher, Mowery and Simco, 2002). Yet, with growing complexity of SoC design, decoupling became impractical. A combination of new processes and drastic changes in design methodology implies that design rules need to be tweaked and stretched, and that process limitations are there “to be explored not worshipped” (Wilson, 2003: 63), requiring a much closer interaction between designers and process engineers. From the perspective of foundries, for instance, nanometer process technology makes yield enhancement much more difficult for 20 to 50 million transistor SoCs (interview with Taiwanese foundry). As processes grow more demanding, mask makers and process engineers will try to pass this growing complexity to the chip design team through an enormous increase in complexity in either cell selection or design rules. And the foundry’s process engineers now include into the design rules for SoC designers the request to “design-for-yield-enhancement.”

This new interface requirement means that design teams must adjust the design to improve the odds that the process will yield well and that the dice will continue working even under demanding system performance requirements. In other words, designers must take into account the effects of fabrication process variations, which makes design even more complex. There is now a much greater need for dense interaction between physical designers and process integration teams; and designers increasingly must take into account the intricacies of process development. An “extraordinary degree of coordination” is required between SoC designers, mask makers, foundries, and third party SIP suppliers (EEdesign, 2003b). As the world’s leading foundries are all based in Asia, this creates powerful pressures for GDNs to relocate increasingly important stages of chip design to this region.

In short, chip design has become itself a highly complex technology system, where multiple communication and knowledge exchange interfaces must be managed simultaneously. SoC design requires a large number of designers with multiple, highly diverse capabilities. Hence, geographic proximity can become a disadvantage for innovative activities that involve complex technological knowledge. This is confirmed in the interviews. Global firms emphasize that it becomes increasingly costly to bring together a large group of very diverse people at one location, and to keep it there. When concentrated in one location, especially in the home country, such design groups may become too powerful, which may constrain productivity growth. But once they become dispersed, this creates extremely demanding coordination requirements for managing multiple chip design interfaces. Vertical specialization within GDNs is an attempt to provide an efficient and flexible organizational environment for the exchange of design knowledge across diverse design communities that are not co-located.

5. Pressures and Opportunities for Moving Chip Design to Asia

We now turn to the final missing link of our analysis, and explore the pressures and opportunities that vertical specialization is creating for GDN participants to move chip design to Asia.

5.1. Direct impact of changes in design methodology

Recent changes in design methodology in response to the “SoC crisis” have pushed vertical specialization still deeper into the design value chain. Take “platform design”, an attempt to reduce the time required and risk involved in designing and verifying a complex SoC, by systematically reusing as many design steps as possible (Chang, 2003). Platform design attempts to capture and reuse not just individual design building blocks (SIPs), but the “best architectures and design approaches found for particular types of products and markets… (Platforms) “crystallize and harden these approaches for reuse by others.” (Martin, 2003: 13).This increases the spatial mobility of chip design. Once a library of “best architectures and design approaches” exists, this can facilitate the exchange of knowledge “from more experienced design teams and architects to less experienced designers.” (Martin, 2003: 13). Platform design thus enables the disintegration and geographic dispersion of design teams to multiple locations with different, yet complementary specialization profiles. Interview responses show that this may accelerate the relocation of chip design to Asia.

“Embedded software (ESW) design” provides a second example of how changes in design methodology can push the dispersion of chip design to Asia. ESW design is the “next bottleneck” in SoC design: “the amount of software - for applications like multimedia cell phones, PDAs, and digital televisions - is increasing exponentially, while the efficiency of software design is not keeping pace.” (Claasen, 2003: 24) This has drastically increased the share of software design costs. For instance, to implement a 20 million gate design at the 90 nanometer process technology, the software design costs are substantially higher than hardware design costs, i.e. $ 30 million out of a total of $ 52 million (IBS 2002: 67). As both IDMs and design houses typically have insufficient software designers (IBS 2002: 57), they are forced to search worldwide for ESW capabilities. In the interviews, global firms indicate a significant potential for outsourcing ESW to the sprawling software engineering clusters in Asia, primarily in India and Greater China.

5.2. Skill requirements and work organization

In addition, drastic changes in the nature of design work create powerful pressures to move chip design to Asia. Design is not just done faster, it is done differently by different people, and vertical specialization has fundamentally altered the relationship between designer and design. SoC design teams need to be able to recruit and retain highly experienced design engineers who master a portfolio of critical skills and capabilities and who are willing to adjust to the new requirements of SoC design. Such design talent is scarce everywhere, and hence SoC design teams need to recruit and retain them wherever they exist, and this is increasingly in Asia.

A widely quoted study prepared for the Electronic Design Automation Consortium, highlights the “limited number of engineers available worldwide to implement complex designs” as a critical challenge to SoC design (IBS 2002: 13). This “designer bottleneck” reflects a growing gap between what designers expect to earn and what design firms are willing to pay. During the “New Economy” boom of the 1990s, U.S. designers were used to receive generous stock options and other incentives. Since the downturn however, practically all non-Asian firms in the interview sample had to drastically cut remuneration.

The “designer bottleneck” also reflects a serious mismatch between the supply of skills in the existing designer population and the quite different skills required by the transition from board-level to system-level chip design. A majority of the designer population are board-level designers. The skills they have honed over the years are very different from the new skill set required for SoC design. Some board-level designers may find niches to survive in design teams of global system companies. But most board-level designers will have to go through a difficult process of unlearning and re-learning. For instance, quality requirements are much more demanding: with SoC mask sets costing up to $ 1 million, design quality must adhere to “right first time” methodologies. While a board designer must be good in tweaking design prototypes, this is no longer possible with SoC design. Instead of tinkering, based on accumulated design experience, much more abstract thinking is required. A particularly demanding change in skill requirements is that SoC designers need to be much more knowledgeable about the use of software tools. As design methodologies are still in flux, designers must adjust to abrupt changes in design procedures.

In response to these changes in design skill requirements, a thriving market has emerged for design training and re-skilling services by EDA tool vendors, specialized private training organizations and public research institutes. Asia’s leading electronics exporting countries have been quick to develop their own private and public SoC design training institutions to accelerate the development of new specialized chip and system design clusters. And these efforts are showing results, attracting support from leading EDA tool vendors. An important finding of the interviews is that Asian designers are being trained using the latest tools and methodologies. Once Asian designers have gained practical experience, this may give them an advantage over designers in the traditional centers of design excellence in the US.

Interview responses emphasize that the transition to SoC design requires working conditions that are alien to the “Silicon Valley” culture. The highly routinized, almost factory-type organization of SoC design work contrasts sharply with the self-perceptions of IC designers in the US and Europe. For them what counts in their resumes is to have “authored” original “breakthrough designs”, by pushing the envelope of design methodologies. These ambitions are frustrated by the move towards more structured design approaches that emphasize incremental progress through the reuse of existing SIPs. Many designers complain that this “just doesn’t look great on a resume.” SoC design also erodes an erstwhile artisan-type design operation. Board-level designers are used to work in small teams and to see a whole design through to completion. Yet, SoC designs tend to be done in very large teams, spread across different countries and time zones. The typical team size for an SOC design can range from 50 to 60 engineers (up from around 10 for board-level design). And to complete an Intel processor design can take two years and involves thousands of people in different countries, which requires a highly structured and disciplined factory-type work process (Collins, 2003:9). This is so, because with growing team size and with geographic dispersion of design teams, coordination costs rise, comprising now around 20 to 30% of the total design implementation costs (IBS 2002: 67).

Most important however are changes in design procedures to improve design productivity and time-to-market, which gives rise to an intense workload. SoC designers “work six days per week, twelve hours per day, with intense pressures to meet the time-to-market requirements for design” (IBS 2003: 42). Obviously a 72 hours work week will come at the cost of innovation, even if incentives through stock options are high. But as pressure grows in the U.S. to expense stock options, it is difficult to see why designers there would be willing to keep up with such health-destroying work loads. That may be different however in Taiwan and China, where the system of personal income taxation enables semiconductor personnel to receive company stock and options as compensation in a manner which results in little or no actual income or capital gains tax being paid when the stock is sold. As a result, Taiwanese and Chinese firms arguably “have a competitive advantage … with respect to competition for talent that other firms cannot match.” (Howell et al, 2003: IV)[22].

Finally, attempts to reduce resistance to the transformation of design work into a factory-type operation provide an additional powerful push factor for moving chip design to Asia. A critical challenge posed by the transition to SoC design is to develop an organizational set-up that facilitates the exchange and reuse of design knowledge. Apparently, the reuse of design knowledge is spatially sticky: knowledge reuse works well, as long as this knowledge is embedded in individual designers, or small specialized design teams. One way to do this is to place everyone literally in one room. The so-called “boiler room” model, where dense informal contacts between designers result from having coffee and lunch together, is unbeatable when the objective is to exchange complex tacit knowledge (Wilson, 2003: 49). A second approach is the so-called “journey men” model, where successful design teams tend to stay together, moving as a group from one company to another, or to new locations. Sometimes, these design teams even tend to maintain the same SIP vendors from job to job, “preserving interfaces that have evolved through trial and trouble and that have come to be trusted.” (Wilson, 2003: 62).

In both cases, what is reused is the knowledge in the team members’ heads, as well as their experience with the processes, tools, and technology they used. But once another engineer or another engineering team is asked to reproduce this design, little productivity increase is observed. One possible explanation may be that cultural and behavioral barriers to the reuse of design knowledge are deeply entrenched in particular localities. The interviews indicate that chip design engineers in the US have a tendency to invent wherever possible, rather than to simply reuse existing SIPs. This so-called “not invented here” syndrome is difficult to change, as it reflects the pride of an engineer who has found a more elegant design solution. Other such barriers include an unwillingness to accept a heavily constrained environment (a “design factory”), or an inability to create an acceptably constrained environment (Chang et al, 1999, p.18).

In contrast, designers in Asia, who have been trained to use the latest tools and SoC design methodologies, do not share these legacy problems. In the interviews, global firms indicated that attempts to bypass resistance to SoC design have played an important role for the relocation of chip design to Asia.

Conclusions

This paper explored why chip design that, in Pavitt’s framework is not supposed to move, is moving from the traditional centers to a few new specialized design clusters in Asia. I use a conceptual framework that draws on insights from three separate literatures, which despite their close relationship have rarely been brought to bear on each other: foreign direct investment (FDI) and multinational corporations; economic geography; and internationalization of innovation. Specifically, I distinguish “pull”, “policy” and “push” factors to examine what forces are behind the growing geographic mobility of chip design, and its dispersion to Asia.

I demonstrate that pull and policy factors can explain what attracts chip design to particular locations in Asia. However, they do not explain what tilts the balance in favor of geographical decentralization. “Push” factors are used to examine why chip design, despite its extraordinary complexity, can now be conducted at multiple locations. The paper describes how changes in the methodology and organization of chip design that were introduced to improve design productivity, instead have further increased the cognitive and organizational complexity of design. In response, vertical specialization within GDNs has been pushed deeper and deeper into the design value chain.

In contrast to earlier expectations of arms-length “frictionless” contracting in chip design, I show that GDNs are long-term arrangements that are shaped by corporate strategies. Initially, this has loosened the bonds between design and fabrication, with GDNs centered on the well-known symbiotic fabless/foundry relationship. Over time however, vertical specialization has increased the number and variety of GDN participants, business models, and design interfaces, bringing together design teams from companies that drastically differ in size, market power, location and nationality. This has dramatically increased the organizational complexity of these networks -- GDNs must simultaneously coordinate multiple communication and knowledge exchange interfaces.

The paper demonstrates that, as SoC design requires a large number of designers with highly diverse capabilities, geographic proximity can become a disadvantage. I document pressures and opportunities that vertical specialization has created for GDN participants to relocate design to Asia, highlighting specifically the increasing importance of software design, as well as changes in skill requirements and in design work organization.

These findings shed new light on the link between complexity and internationalization of innovation. They confirm key propositions of Granstrand et al (1993) and Cantwell (1995): under certain conditions, the “centrifugal” forces for geographical decentralization can be stronger than the “centripetal” forces for geographical centralization, creating and linking together multiple locations for innovation. However, more work is needed to establish the precise nature of these conditions. Pavitt’s framework can help to reduce this gap in our knowledge. His arguments for proximity and co-location of innovation remain as powerful as ever. But we need to reconcile these arguments with new empirical evidence (like in this paper on chip design). Pavitt’s request that “new theories emerge from new data” defines the challenge for innovation theory --- we need to explain what makes it possible to exchange complex knowledge even if innovation agents are located at distant locations.

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[1] This draws on Ernst, 1997, 2002b and 2003. See also work on value chains (e.g., Gereffi, Humphrey and Sturgeon, 2004) which however does not explore innovation.

[2] Of the 234 Taiwanese chip design companies (Nanda, 2003), five are among of the top 20 worldwide fabless companies. And two Taiwanese design houses have moved up to the number 5 and 6 spots, capturing 16% of global fabless revenues.

[3] Figure 3 below illustrates what a GDN looks like.

[4] The small size of the sample, relative to the large number of strategic groups covered, does not allow to perform a statistical analysis. However, the interviews provide extremely valuable qualitative insights that can guide future research.

[5] “Architecture” refers to “the partitioning of the … (computer) … system into components of a given scope and related to each other functionally and physically through given interfaces. From a given architecture flows the design of components’ functions and how they relate to each other…” (Gawer and Cusumano, 2002: 18).

[6] This corresponds with findings of the 2004 Electronic Engineering Times surveys: Korean firms lead in terms of the gate count of leading-edge SoC designs, while Taiwanese firms are ahead in the line-width of process technology (Kou, 2004; Park, 2004). On both measures, Chinese firms rank third (Zhang, 2004)

[7] “Platform leadership” strategies are defined by decisions on the “system architecture (the degree of modularity), interfaces (the degree of openness of the interfaces to the platform), and intellectual property (how much information about the platform and its interfaces to disclose to outside firms)” (Gawer and Cusumano, 2002: 40). These strategies have two objectives: to avoid the very high costs and risks of trying to develop complex technology systems in-house; and to enhance and control patterns of innovation in an industry. The over-riding purpose of these strategies is to leverage the existing market power of industry leaders into the control of “systemic architectural innovations” (Gawer and Cusumano, 2002: 39). A typical example are Intel’s attempts to extend its control over microprocessors by creating widely accepted architectural designs that increase the processing requirements of electronic systems, and hence the market for Intel’s microprocessors.

[8] Similar findings are reported in Armbrecht, 2003, von Zedwitz, 2004, and Walsh, 2003.

[9] During my interviews, chips designed by foreign and domestic companies in China were eligible for a 14% VAT tax rebate, which lowers the effective tax rate to 3%, from the nominal VAT of 17% on sales of imported and domestically produced chips. This policy which created a powerful artificial cost advantage for domestically designed chips, was later abandoned under pressure from the US government.

[10] This supports earlier findings in the literature, e.g., Shen, 1999; Lu, 2000; Naughton and Segal, 2003; Mathews and Cho, 2000; Hobday, 1995; Ernst, Ganiatsos and Mytelka, 1998; Ernst and O’Connor, 1992; Ernst, 1994 and 2000.

[11] Taiwanese firms develop “slightly more complex designs on average at slightly higher design productivity rates” than Chinese firms (Nanda, 2003: 11,12). However, even these relatively small differences in design complexity and productivity can provide very substantial rewards: Taiwanese design houses paid roughly three times as much as their Chinese counterparts.

[12] The TD-SCDMA standard was developed by Datang Telecom, a Chinese state-owned enterprise, and the Research Institute of the Ministry of Information Industry, with technical assistance from Siemens. To accelerate implementation, Datang has formed a series of collaborative agreements: a joint venture with Nokia, Texas Instruments, the Korean LG group, and Taiwanese ODM (= original design manufacturing) suppliers; a joint venture with Philips and Samsung; and a licensing agreement with STMicroelectronics that will provide the Chinese company with access to critical design building blocks (Ernst and Naughton, 2004).

[13] See also related work by Chuma, 2004 and Tokumaru, 2004

[14] “Design methodology” is the sequence of steps by which a design process will reliably produce a design “as close as possible” to the design target, while maintaining feasibility with respect to constraints.

[15] “Modular design” is a particular design methodology in which “parameters and tasks are interdependent within units (modules) and independent across them” (Baldwin and Clark, 2000: 88).

[16] This confirms Rosenberg’s insight that the real impact of important innovations is seldom realized immediately, but requires countless iterations and re-combinations with other complementary innovations (e.g., Rosenberg, 1976: ch. 11).

[17] This pressure to focus design on acceptable fabrication yields increases as yields tend to fall quite drastically with progressive process miniaturization (Edwards, 2003: 7)

[18] As discussed in part 3, Asian system companies can afford to be less risk-averse, due to support policies that provide incentives and public goods.

[19] For instance, designing an embedded micro-controller for a mobile handset requires a different GDN configuration than the design of a graphic chip.

[20] An ASIC typically is composed of standard building blocks called “cells” that are designed to implement a specific customer application.

[21] The resulting limits to modularity are examined in Ernst, 2004.

[22] In Taiwan and China, employees of semiconductor firms who have received stock as compensation are taxed on the face value of the shares, not the market value - which is often many times higher than the face value, given the rapid growth of semiconductor firms in both countries.

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