Calypto Design Systems Inc. announced that Virage Logic’s 45-nanometer (nm) and 28nm SiWare Memory compilers now automatically generate PowerPro MG power optimization models for reducing System-on-Chip (SoC) embedded memory power. This support is the result of a collaboration between the two companies to reduce on-chip SoC memory power. Using PowerPro MG, designers can reduce both dynamic and leakage power, resulting in up to 80 percent memory power reduction compared to previous implementations.

Virage Logic delivers memory compilers that enable SoC designers to explore the tradeoffs between performance, area, power and statistical yield to generate optimal memory configurations. The latest release of the 45nm and 28nm SiWare Memory compliers will now automatically generate PowerPro MG models. This enables design teams to easily integrate PowerPro MG into their fully automated design flows to reduce both dynamic and leakage memory power.

Using Calypto’s sequential analysis technology, PowerPro MG constructs new memory gating logic that works in conjunction with the low-power memory modes to produce the lowest power memory implementation possible. PowerPro MG then generates new power-optimized RTL that looks identical to the original RTL except for the addition of the new memory gating logic. PowerPro MG reduces dynamic power by automatically generating logic that controls the memory enable signal and eliminates unnecessary memory accesses. PowerPro MG reduces leakage power by automatically generating logic that controls the sleep modes of individual embedded memories.

Available now, Calypto’s PowerPro MG runs on PC platforms running Linux and is priced at $295K for a one year time based license.