SpringSoft, Inc. has announced that VeriSilicon Holdings Co. Ltd. has selected its Verdi Automated Debug System as the standard debug platform. The Verdi software is currently being deployed by VeriSilicon's worldwide research and development (R&D) organization and implemented in its debug reference flow to significantly reduce debug time and accelerate functional verification of complex digital IC and system-on-chip (SoC) designs at advanced technology nodes.

"As a leading design service company, VeriSilicon is continuously honing and improving our design and verification flow. Verdi is a very important tool in the flow that enables us to deliver the best-in-class design service quality and enhance our overall verification competency", commented James Jiang, corporate vice president of engineering for VeriSilicon.

VeriSilicon has already integrated the Verdi platform into its production-proven verification flow for most digital design projects. The Verdi tool suite and design analysis capabilities are used today by all VeriSilicon design engineers responsible for functional verification during both pre- and post-layout simulation. With the ability to visualize the hierarchy and relationship of a design from multiple views, VeriSilicon engineers are able to quickly locate problems and trace root causes, reducing debug cycles by 20 percent on average across its broad range of design applications.

The Verdi Automated Debug System is SpringSoft's flagship product for advanced debug. It cuts debug time in half by automating the process of comprehending how complex IC and SoC designs work, particularly unfamiliar legacy design elements or third-party intellectual property. The full-featured system automates behavior tracing over time with its unique analysis engines, provides a powerful set of design views to visualize and help analyze cause-and-effect relationships, and uses patented techniques to reveal the functional operation and interaction between the design, assertions and system
testbench.