The Tuesday morning Accellera breakfast at DAC has become a tradition and a test of the serious intentions of DAC attendees. After a busy Monday and an evening of intense networking showing up for breakfast at 7:30 in the morning is not easy. But many do it and they are rewarded. Not just for the food, mind you, but by the interesting panel that follows. The event will take place in room 203B of the Anaheim Convention Center and will last until 9:00 AM.

This year the panelists will discuss one of the latest Accellera projects: UVM. The panelists include:

Sharon Rosenberg, Verification Solutions Architect, Cadence
Hillel Miller, Verification Manager, Freescale and VIP-TSC co-chair
Mohamed Elmalaki, Verification Expert, Intel
Tom Fitzpatrick, Verification Technologist, Mentor
Janick Bergeron, Synopsys Fellow, Synopsys
Stacey Secatch, Sr. Staff Design Engineer, Xilinx

The panel is hosted by Shrenik Mehta, Chairman of Accellera and will be moderated by Gabe Moretti, one of the founders of Accellera and owner of GABEonEDA.

The principal motivators of the UVM project, Stan Krolikoski of Cadence, Dennis Brophy of Mentor, and Yatin Trivedi of Synopsys have authored the following introduction to the subject.

It is no news when one talks about increasing complexity of designing the SoC devices, and it is a foregone conclusion that designing is a relatively bounded problem compared to verification. Just as Design Reuse through Semiconductor IP (aka Design IP) helped bring the designers up the productivity curve, in last decade Verification IP has done the same for the verification engineers. Two leading methodologies, VMM and OVM, helped adoption of structured verification methodologies in SystemVerilog as well as creation of commercially available Verification IPs to independently validate integration of Design IPs in SoCs. Essentially, both methodologies are a collection of SystemVerilog classes with inherent semantics for their behavior in different phases of the simulation. The user creates verification objects from these classes and attaches them to the design components as traffic/data generators, monitors, checkers, etc.

Both verification methodologies are built on SystemVerilog, both have been available under Apache license, and both have been successfully deployed in production environments – with one caveat, as long as the verification IP was built on only one of them and not the other. This is where the problem arises. Many projects acquire Verification IP (VIP) from multiple vendors, and occasionally even multiple groups inside a company may have worked independently using different methodologies. Naturally, there is a conflict for integrating such VIPs into one consistent verification environment.

Back in 2007-08, this was recognized as an issue, and leading users formed Verification IP Interoperability committee (VIP-TSC) under Accellera. By July 2009 twelve best practices were formalized in form of an API to allow interoperability of VMM and OVM VIPs in a single environment. These best practices were published as Recommendations for VIP Interoperability. However, it was only seen as the first step in solving a larger problem – that of having publicly available universal base classes that can be used for creating wide variety of VIPs. Naturally, if all VIPs are based on the same base class library, one does not need to go through interoperability API. Thus came to life the second phase of VIP-TSC – Universal Verification methodology (UVM).

UVM base class is still based on SystemVerilog. OVM 2.1.1 has been used as the starting point to define UVM. In the Early Adopter release of the UVM (UVM-EA), there were some enhancements to Callbacks and End-of-Test features, and a new type of Message Catcher callback was added, along with renaming of objects to UVM_*.The VIP-TSC has a list of items that brings features from OVM, VMM and other home-grown methodologies to add to UVM-EA for release 1.0 and beyond. However, current and planned features of UVM base class can be best described as the reflection of collective knowledge of the verification experts participating in VIP-TSC.

In other words, are we just transferring the knowledge from syntactically and semantically different methodologies into a new one? What is the real value to this exercise? If we fast forward by a year, what would UVM base class release X look like? What features should it have to solve the problems faced a year from now? 3 years from now? Are we looking at adding more of the same or make a quantum leap in our ability to deal with much larger and significantly more complex designs? What specifically are we doing to improve our ability to find bugs in the design and then fix them?

This is the topic of breakfast discussion at DAC, hosted by Accellera and sponsored by its corporate members Cadence, Mentor and Synopsys. The panelists are all verification experts from the user and vendor community who are known to compete feverishly but also demand the most comprehensive solution. Of course, the moderator is no stranger to challenges and stimulating great dialog across the industry. Time for you to find out and even chime in.

I hope to see you there.