Last week I wrote that TSMC had validated Synopsys' design flow on its 3D-IC process. Today I received a press release from Cadence stating fundamentally the same thing with regard to its design flow. It is clear that work on 20 nm processes is intensifying as a way to justify the significant investment required by system companies to use it.
The fundamental problem is not "just" tools. Of course tools enhancements are required, and they are anything but trivial. But what is more important is that a change is required in the way architects and engineers approach the planning and development of an IC that must take as much advantage of the process as possible. The problem is that while even with 32 nm processes one could make modification late in the development stage, the rules at 20 nm are so many and so strict that making even a small change can begin a chain process that will take the development team practically back to the beginning of the project.
Clearly this is a cost that cannot be tolerated, and the investment in time to fix the problem is likely to make it impossible to meet the market window. The project, then, becomes scrap.
The 3D method is an attractive way to shrink the IC footprint and even save power. But it is yet a leading edge method. Expert availability is practically non-existent, and development teams are working at the boundary between research and engineering. Yet, both Cadence and Synopsys now have managed to provide reliable design flows for TSMC's CoWoS process.
TSMC's CoWoS is an integrated process technology that bonds multiple chips in a single device to reduce power and form factor while improving system performance. Cadence 3D-IC technology enables multi-chip co-design between digital, custom and package environments incorporating through-silicon vias (TSVs) on both chips and silicon carriers, and supports micro-bump alignment, placement, routing, design for test, as well as analysis and verification from a system perspective. The Wide I/O controller and PHY demonstrate the advantages of implementing memory subsystems on 3D-IC technology for increased memory bandwidth with significant reduction in operating power.
The Cadence Details
The validated technologies in the 3D-IC solution span the Cadence Encounter RTL-to-signoff and Virtuoso custom/analog platforms. Also included are the Cadence system-in-package products, and recently acquired Sigrity power-aware chip/package/board signal integrity solution that helps engineers overcome die-stacking and silicon carriers' challenges from planning through implementation, test, analysis and verification. TSMC's unique CoWoS combo bump cells, which simplify bump assignment, are now supported automatically in the Cadence Encounter Digital Implementation (EDI) System, QRC Extraction, and Cadence Physical Verification System. The CoWoS Reference Flow is supported with a CoWoS design kit and silicon validation results from a TSMC test vehicle.