Synopsys took two major steps in the prototyping market segment during DVCon. First it released a new prototyping board, the HAPS-600 and then, the following day, it announced the release, in collaboration with Xilinx, of a FPGA-Based Prototyping Methodology Manual(FPMM). The product and the manual complement the family of virtual prototyping tools that Synopsys already offers. Thus software developers are now supported through the entire life of a prototype, enhancing the ability to develop embedded software in parallel with the SoC hardware. Synopsys plans to create a community of practicing prototyping engineers and users around the book.
Methodology Manual for FPGA-Based Prototyping of SoC Designs
The FPMM is a practical guide to using FPGAs as a platform for system-on-chip (SoC) development. The FPMM captures design and verification expertise contributed by engineering teams from BBC Research & Development; Design of System on Silicon, S.A. (DS2); Freescale Semiconductor; LSI, Inc.; NVIDIA Corp.; STMicroelectronics; and Texas Instruments (TI), which have successfully employed FPGA-based prototyping to accelerate complex ASIC and SoC development projects.
The manual covers all aspects of FPGA-based prototyping, including understanding the challenges and benefits of prototyping, the implementation of a SoC design in FPGA, and finally, its use for software and system validation. Synopsys and Xilinx expect the FPMM to be the catalyst for an online, interactive FPGA-based prototyping community, hosted at http://www.synopsys.com/fpmm, where prototypers can raise challenges and exchange best practices.
FPMM authors Doug Amos and René Richter of Synopsys and Austin Lesea of Xilinx are experts in FPGA technology and prototyping of designs using FPGAs. Recognizing that SoC designs are usually created for ASIC technology implementation, and therefore present specific challenges for implementation in one or more FPGA devices, the authors created a unique reference guide that will help not only first-time prototypers, but also experienced teams and project leaders. In addition to surveying the range of prototyping options, from virtual prototyping through building custom boards to purchasing complete prototyping systems, the FPMM outlines a methodology called Design-for-Prototyping. Design-for-Prototyping integrates FPGA-based prototyping seamlessly into the ASIC/SoC project so that the design can be more readily implemented and made available at the earliest opportunity to the end-users. This approach delivers productivity benefits by connecting to system-level tools like virtual prototyping for earlier software development and during the crucial later stages of a project when hardware and software are integrated for the first time.
The FPMM contains 15 comprehensive chapters and two appendices that cover real-world examples. The manual is organized into chapters that parallel the tasks and decisions faced during an FPGA-based prototyping project. The chapters are also designed to stand alone, allowing the manual to be used as a reference.
For more information on the FPMM, including how to purchase a copy through Amazon.com or to download a free eBook version, please go to the FPMM website at http://www.synopsys.com/fpmm. Additionally, to learn more about the other methodology manuals and educational publications produced by Synopsys Press, visit http://www.synopsys.com/synopsyspress.
HAPS-600 Series Offers High Flexibility and Scalability
HAPS®-600 series is the highest capacity extension of the HAPS family of FPGA-based prototyping systems. The HAPS-600 series extends FPGA-based prototyping capacity up to 81 million ASIC gates equivalent, enabling early software development for larger SoC projects. Like the HAPS-60 products, the HAPS-600 series is based on Xilinx Virtex®-6 LX760 FPGA devices and offers performance up to 200 megahertz (MHz).
The HAPS family provides an integrated and scalable hardware plus software solution that is used by hardware and software design teams to develop software, verify SoC hardware and enable hardware/software integration before tape-out. Designers can reduce initial turnaround times and subsequent iterations with the HAPS-600 series' highly automated software flow from ASIC RTL code to the FPGA-based prototype utilizing Synopsys' patented programmable switch routing technology.
Like the HAPS-60 series, the HAPS-600 series includes native integration of the Universal Multi-Resource Bus (UMRBus) which allows users to ease system bring-up with co-simulation capabilities. The UMRBus also accelerates system-level verification with SCE-MI 2.0 transaction-based verification and provides links to Synopsys' virtual prototyping solution. In addition, the HAPS-600 series offers enhanced design visibility reducing debug time as well as remote prototype management improving productivity for globally distributed teams. Design teams also benefit from the HAPS-600 series' support of Synopsys' DesignWare® IP, which ensures that the same IP code used in the design is also available within the FPGA-based prototype.