The Mathworks, a company that until three years ago was practically unknown in the EDA industry, has been the leader in system level design for many years. It has developed such concepts as Model Based Design, and the MATLAB language used by most designers of communications and multimedia systems. Synopsys has now introduced the Synphony high level synthesis product that allows to transform MATLAB code into RTL.

The Synphony HLS (High Level Synthesis) solution, launched officially today, integrates MATLAB language based design and model-based synthesis and aims to improve the productivity of design and verification flows over traditional RTL methods for communications and multimedia applications.

Synphony HLS creates optimized RTL for ASIC and FPGA implementation, architecture exploration and rapid prototyping. In addition, Synphony HLS complements C/C++-based flows by generating C-models for system validation and early software development in virtual platforms. Synphony HLS integrates with Synopsys’ established flows that take algorithms development to silicon.

As can be seen from Figure 1 below the algorithmic development and verification takes place in the Mathworks environment. The orange numbers in the figure identify specific flow points described below.

Figure 1
The Mathworks’ MATLAB environment has been broadly adopted for algorithm exploration and design because it allows concise expression of behavior at an extremely high level of abstraction. The MATLAB language models developed in this environment are typically recoded and re-verified at the RT Level (RTL) and in some cases in C/C++ for implementation and verification. Unlike inefficient and error-prone manual re-coding flows, Synphony HLS creates implementable RTL and C-models directly from high-level MATLAB language code (1) and the Synphony HLS-optimized IP model libraries (2). Using a unique constraint-driven fixed-point propagation feature (3), designers can quickly and intuitively derive fixed-point models from a synthesizable subset of high-level, floating-point MATLAB code. The Synphony HLS engine will then synthesize architecturally optimized RTL (4) to meet area, speed and power goals. Finally, by creating a C language model (5), Synphony allows designers to stay in their preferred algorithm modeling language, eliminating the need to re-code and re-verify models and enabling early system-level validation and verification.

Synopsys Enhances Design Flow

The Synphony HLS engine can synthesize optimized architectures for ASIC, FPGA, rapid prototyping or virtual platforms while maintaining coherent verification through all levels of the implementation flow. Given the user-specified target and architectural constraints, the HLS engine automatically optimizes at multiple levels by applying pipelining, scheduling and binding optimizations across language and model boundaries, including MATLAB language, IP blocks and throughout the design hierarchy (Figure 2).

Figure 2
Synphony HLS includes a new advanced timing estimation capability that automatically utilizes Design Compiler for accurate information needed in automatic pipelining and rapid timing closure for a given ASIC technology. The tool includes advanced timing and device-specific optimizations for a broad range of FPGA families. This includes optimized mapping to hardware multipliers, memories, shift registers and other advanced hardware resources in today’s FPGA devices.

Synphony HLS increases the value of Synopsys’ Confirma rapid prototyping solutions, by improving the flow used by design teams to create a pre-silicon prototype of their design and start algorithm validation and software development much earlier in the design cycle.

Synphony HLS complements C/C++ implementation, verification and embedded software development flows by making C-model creation a natural byproduct of the development flow. Synphony HLS generates fixed-point ANSI-C models that can be used in a variety of system simulation environments and virtual platforms including Synopsys’ Innovator, System Studio, VCS and SystemC flows. Thus Synphony HLS enables C-based verification and validation to start much earlier in the design cycle.

Packaging and Availability

Synphony HLS includes MATLAB synthesis technology, C-model generation, the Synphony HLS high level IP model library and the Synphony HLS engine for ASIC and FPGA. Synphony HLS is now in limited customer availability with general availability by the end of calendar year 2009. For more information please visit the Synphony web page.