On the tail of Mentor’s transfer of Catapult C to Calypto, Synopsys, Inc. announced availability of the latest release of its Synplify Pro and Synplify Premier FPGA synthesis tools.
The company states that the new Synplify tool release enables engineers to build higher reliability into their FPGA designs through a new feature that provides automated creation and preservation of error-correction logic, including safe finite-state machines (FSMs). Additionally, an enhanced interface for the tool allows designers to track progress and analyze synthesis results hierarchically. For ASIC prototypers, support for Synopsys DesignWare Library MacroCell IP has been added, broadening DesignWare IP support and improving compatibility with Design Compiler.

Overall both efforts to built in error correction and to increase compatibility with Design Compiler are good moves by Synopsys. Today’s FPGA devices ar so large that the overhead introduced by inserting error correction logic will not degrade the functionality by any discernable amount, nor will it resolve in an overflow of the circuit forcing the use of an additional device.

The 2011.09 Synplify software release gives designers the ability to create designs that are resistant to single event upsets (SEUs) by including an option for designers to automatically preserve sequential logic. Synplify Premier also automates implementation of 1-hot safe FSM error detection circuitry, further increasing in-field system reliability of FPGA devices. To improve productivity in implementing large-scale designs, the new Synplify software release expands on the tools' hierarchical design flow capability with a new GUI interface. The interface allows users to intuitively validate and view synthesis settings prior to synthesis and then centrally monitor design progress hierarchically. Also, the latest Synplify software will automatically convert gated and generated clocks that cross hierarchical boundaries in an ASIC design into equivalent FPGA structures.

In addition, the latest release of Synplify Premier now synthesizes encrypted DesignWare Library MacroCell Infrastructure IP. As a result, these encrypted RTL cores can now be read directly by Synopsys' FPGA and ASIC implementation tools in addition to verification tools, allowing ASIC designers to seamlessly prototype their ASIC designs in FPGAs. The newly supported DesignWare Infrastructure IP includes ARM AMBA 3 (AXI, AHB, APB) interconnect, APB advanced peripherals, APB peripherals, microcontrollers (DW8051, DW6811) and memory controller components.