Real Intent Inc. announced it is now shipping version 1.5 of its Ascent Lint software. The tool analyzes and elaborates a design and generates a report of syntax and semantic errors.

Ascent Lint adds over 40 new rules for Verilog, VHDL and SystemVerilog designs, covering both RTL and gate-level netlists. These checks help catch bugs and improve design quality early in the design cycle.

The user interface has also been significantly upgraded. The new version of Ascent Lint improves usability with enhancements to the lint debugger GUI and lint policy configuration utility, a more robust waiving capability, and better lint documentation. These features offer greater ease-of-use and faster turnaround for designers.