STARC, the Japanese electronic design consortium, has selected Orora’s Arana as the post-layout mixed-signal design verification solution for Japanese semiconductor industry’s next-generation STARCAD-AMS Analog/Mixed Signal reference flow.
Orora Design Technologies, Inc. is focused on developing software tools and solutions for automating mixed-signal integrated circuit design and verification. Founded in 1998, the company is privately held. The company is headquartered in Issaquah, Washington.
Orora has been a DAC exhibitor for the last few years, but, as most emerging EDA companies behave, has not had the opportunity to avail itself of professional communication professionals. As a result its outstanding technology which I covered a couple of years ago has not grabbed the headlines. One had to seek out their 10X10 booth, and listen to what the few engineers manning the booth had to say. No marketing speeches, no cute give away, just solid technology.
As most readers know, STARC (The Semiconductor Technology Academic Research Center) is a consortium founded in 1995 by leading Japanese semiconductor companies. STARC's mission is to contribute to the growth of the Japanese semiconductor industry by developing leading-edge SoC design technologies.
Analog model generation presents very difficult technical problems, as evidenced by the slow growth of analog synthesis. Arana has impressed me for its ease of use. I am not an analog engineer, yet I could easily follow the process, since what is revolutionary is hidden below a schematic interface that is quite intuitive.
Kunihiko Tsuboi, Senior Manager of STARC's Development Department-2, noted that " With next-generation analog and mixed-signal circuits being more sensitive to process, voltage and temperature (PVT) variations, and parasitic effects, the increased use of digital control for compensating analog circuitry imperfection and digital configuration for system-level programmability, we see that the time and cost for post-layout mixed-signal design verification are sky-rocketing."
Tatsuya Shirakawa, Researcher of STARC’s Mixed-Signal Design Group added that "For STARC motif benchmark, Arana can automatically generate all PVT-aware behavioral models from a post-layout netlist, and reduces the post-layout simulation time by more than 200 times with less than 1% accuracy loss."