Shankar Krishnamoorthy, division chief scientist at Mentor Graphics talked about "The New Challenges of Advanced SoC Implementation" in a keynote address at the International Symposium on Quality Electronic Design (ISQED). The convergence of computers, communications, and consumer products is the driving force for increases in size and complexity in SoC designs.

New processes will always create new challenges for the designers and for physical implementation. The next generation tools will need the ability to manage a much broader range of details, and will require new architectures and databases. As device manufacturers move to 40 nm and below, they're finding increasing challenges in the implementation phase of the design. Users are finding that pattern fidelity is exacerbating the problems with device variability. In addition, the designers are rapidly adopting low-power design techniques which further increase both the size and complexity of the designs.

In the past, implementation engineers only needed a small number of models to address the significant corner cases of the process. Now, the number of corner cases coupled with a mixture of modes of operations and multiple voltage islands generate further complexity. For example leakage is dominant in a different corner than set up times or hold times. Taken together, these effects are greatly increasing the time to completion in physical design.

Existing tools approach the problems in piecemeal fashion and generally only address one problem at a time. Current design practices require simultaneous optimization over temperature, voltage, multiple voltage islands and power gating, at the same time that interconnect must be optimized to minimize length and congestion. Unfortunately, separate tools for each of these problem areas results in a chaotic design flow - a fix in one area causes new problems in another. The overall result is longer and more ECO cycles.

Existing place and route architectures are based on timing graphs and use data from the designers and fab to meet constraints with accurate models. The latest processes have many different models and designers are now mixing different libraries within the design to manage both power and performance. The multiplicity of corner cases makes it very hard for the tools to evaluate and address these parasitic issues on the fly. One alternative is to perform some corner compression and work towards a least common denominator type model. This compression and abstraction results in many more ECO's and still does not address problems with signal integrity and manufacturability.

To address low-power design closure, the next generation tools will require concurrent analysis and optimization to look at multiple timing graphs with various models for corners while addressing signal integrity and manufacturability. Low-power design closure must consider all the techniques used in a system-level design and support the IC design teams for low-power, multi-voltage architectures. These tools must have a compact database coupled with power at timing analyses to address the power state tables and the multiple operating modes and models. The optimizations extend deeply into the design, so the tools must be power aware in developing and placing clock trees, down to the leaf and pin capacitance and the wire load. These individually small loads can account for 75 percent of the power consumption in the clock tree.

Large design will continue to take advantage of hierarchical design flows in converting netlists into GDS-II constructs. The size of function blocks will continue to grow, adversely affecting turnaround time, and will require more areas to be fixed for possible violations. Since timing analysis and optimization account for 70 percent of total implementation time, parallel analyses should improve throughput. The advent of multicore computers facilitates the conversion to multiple simultaneous analyses and optimization.

In full chip design closure, the final assembly process is getting much more difficult. The size and complexity of the designs is creating data sets that are unwieldy. A compact data model would reduce data volume and also reduce the size of the memory footprint required to hold a design. Obviously this is a major change in the database, models, and tools, but is necessary to simultaneously look at the full design at multiple levels of abstraction in order to achieve design closure.

On top of the challenges of making an optimized physical design, the final outputs must also address manufacturing closure. As processes continue to shrink, they're getting increasingly complex. Now rule decks include an increasing number of rules that are required, many that are conditional on other rules, and an increasing number of rules that are recommended. This explosion in design rules reflects be tremendous increase in the number manufacturing operations necessary to make a nanometer process wafer. An advance process now takes over a thousand steps for manufacturing.

The problem in achieving manufacturing closure is that current tools evaluate DRC and DFM rules in a batch, post-processing mode. These analyses must be integrated into the place and route flow to reduce conflicts and errors and also improve time to completion. Mentor has introduced an advanced router that integrates Calibre analyses into the layout flow.