Mentor Graphics Corporation announced the new Calibre® RealTime platform for signoff-quality physical verification during design creation. The first release provides instantaneous design rule checking (DRC) in the SpringSoft Laker™ custom IC design and layout solution, using the same Calibre decks as the signoff flow. A version for the Mentor® IC Station® custom design environment will be available in June.
The Calibre® RealTime platform provides instantaneous sign-off Calibre design rule checking (DRC) and design for manufacturing (DFM) to the custom/analog layout engineer during layout creation. Using the same foundry DRC decks used in batch Calibre nmDRC, Calibre RealTime automatically runs Calibre nmDRC in flat mode within the custom design environment whenever geometries or instances are edited. The Calibre RealTime platform improves design speed and quality of results by giving designers, for the first time, the full power of Calibre’s signoff engines and qualified decks during design. Calibre RealTime eliminates the time penalty of the traditional design/check/fix loop, enabling signoff-quality layouts in less time, while allowing engineers to optimize their layouts for performance without sacrificing manufacturing yield. Because Calibre RealTime uses foundry-qualified rule decks, there is no question about correlation between the real-time results and sign-off DRC.
In an attempt to address the need to reduce the amount of time spent fixing DRC errors, custom design tools incorporate a wide variety of built-in DRC tools to assist layout engineers while they are putting down polygons. While all of these proprietary checkers have a similar set of functionality, none of these ‘in-tool’ DRC checkers covers the full spectrum of the sign-off DRC checks, and none is qualified by the foundries for sign-off. As the gap grows between what these built-in DRC checkers can handle and the sign-off decks, layout engineers are spending more and more time iterating to get a clean design and less time on new layout. At 32nm and below, this gap has become very significant, and the difficulty of achieving high-quality, DRC-clean layout is becoming a real business issue for leading edge customers. This gap between what the layout engineers need to do their jobs and what the industry is currently providing provides an opportunity for Calibre to fill a clear need. This is the capability that the Mentor Graphics product, Calibre RealTime, provides.
The Calibre RealTime Solution
Calibre RealTime uses the OpenAccess Run Time Model (OA RTM) to receive notification of change events in the custom design tool, and then to retrieve the appropriate geometries for DRC checking. These geometries are checked by the Calibre nmDRC engine and results posted directly into the design tool interface.
When integrated into a custom IC design and layout system, Calibre RealTime provides direct calls to Calibre analysis engines running foundry-qualified rule decks. These Calibre engines perform fast, incremental checking in the vicinity of shapes being edited, providing nearly instantaneous feedback on design rule violations, as well as potential systematic variation susceptibility as measured by recommended rule compliance.
With its ability to perform all checks that can be run with Calibre DRC, including recommended rules, pattern matching, equation-based DRC, and double patterning, Calibre RealTime lets custom IC designers correct and adjust their designs during the layout process to produce a design that is DRC-clean, resistant to manufacturing variability issues, and optimized for the most desirable performance and operational characteristics.
User-defined custom filters allow designers to limit which checks are run, based on design requirements and organizational processes, without having to modify the foundry qualified rule deck. At the same time, because Calibre RealTime is integrated in addition to the design tool’s built-in checker, users have the freedom to use either or both checking processes, as desired.