Mentor Graphics Corporation has updated its Universal Verification Methodology Connect (UVM Connect) to bring the benefits of it to the Open Verification Methodology (OVM) community. UVM Connect has been extended to allow it to be compiled to run with the OVM. The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With UVM Connect 2.2, teams using OVM can connect with SystemC models and other environments as well.

OVM continues to be a popular and growing methodology for verification teams. About half of all teams have adopted OVM as their verification base-class library and it continues to lead among all other alternatives. To support the OVM community, the Mentor Graphics Verification Academy offers a user community forum and contributions area that encourages users to share their OVM experiences and enhancements with each other. The Verification Academy also has educational and training information to help the novice to the expert.

The enhanced UVM Connect provides standard TLM connectivity between models written in SystemC and OVM SystemVerilog to maximize IP reuse. It is designed to work with all simulators that support the IEEE 1800 SystemVerilog and IEEE 1666 SystemC standards and can accommodate different inter-language instantiation schemes used in various solutions. Feedback from verification teams with simulators from multiple suppliers was taken into account to provide broad industry support.