Dr. Rajeev Ranjan, Chief Technology Officer, Jasper Design Automation

These indeed are interesting times for our industry. We live in a connected world with a new generation of users who demand more and more functionality in smaller and smaller packages. They take high performance and low power for granted, and the semiconductor design ecosystem continues to do amazing work to turn those expectations into reality. I am particularly excited by the role our formal verification technology will play as IC design sizes continue to grow while market windows shrink. One of the main facilitators of this paradigm is IP design and reuse, because now virtually all design starts are SoCs that could never be completed without internal and/or third-party IP.

As a result, formal plays an essential role by providing absolute certainty that there are no hidden bugs, so IP users can confidently integrate these parts into their designs. In addition, reusable IP needs to be highly configurable and formal is able to check for all possible configurations while also ensuring compatibility with different operational modes.

Another breakthrough area is formal verification solutions that let designers explore the functionality of a design and capture its design intent in a persistent and executable database that contains configuration modes, transaction-annotated waveforms representing design functionalities, and more. This database, along with a formal-technology based analysis system, can then be used by the IP consumer to facilitate comprehension, modification and re-verification.

We are also actively working with customers to bring the value of formal to the architectural level, which has the potential to create huge productivity gains by first enabling architects to explore the architecture and establish correctness. The resulting database can serve as an "executable specification" and be leveraged by implementers in developing the RTL code.

Two other applications for formal that proved to be popular topics during our annual Jasper Users Group meeting thanks to their tremendous design-cycle impact are multi-core SoCs and post-silicon debug.

Having multiple processors results in competition for on-chip resources, this in turn results in deadlock and starvation-related issues. Complex memory performance-related design implementations have critical cache coherence protocols verification needs. In general, the issues that used to be handled at the board and socket level must now be dealt with at the chip level, and all can be addressed quite efficiently through formal verification.

For post-silicon debug, the challenge is the lack of visibility and controllability in isolating the root cause of the problem in silicon. Formal can quickly eliminate hypotheses, slashing the time needed to determine the root cause of the design bug, typically saving weeks or even months of lab work. In addition, formal property verification can be applied to insure the correctness of the fix and prevent the introduction of any unintended late-stage design bugs.

To conclude, I have to say I see no end to these "interesting times" thanks to the nature of our work and the endlessly exciting opportunities awaiting us all. Best wishes for a very happy and prosperous New Year!