Maia EDA, based in Cambridge Great Britain, has announced the availability of the Maia functional verification tool. Maia uses a description of the expected behavior of a device to automatically create a complete self-checking reactive testbench. Maia is primarily targeted at hardware engineers who write and need to verify their own RTL code, but a key benefit of the tool is that it can be used by staff who have no knowledge of Verilog or VHDL (although at this time it only supports Verilog), and who have only minimal programming skills.

According to the company, modules and subsystems can be verified by anyone who has access to a specification, and who can construct sequences of vectors corresponding to the device inputs, and expected outputs.

The Maia language arose out of the need to create practical verification tools for real-world design, rather than esoteric system-level tools that have little or no relevance to working Electronic Engineers. The tool has been designed to enable both engineers and non-engineers to quickly verify modules and sub-systems, and is initially being offered without cost by the company, allowing trial without registration or risk.

Maia automates the creation of testbenches by using declarative and fifth-generation language (5GL) techniques. An expected 'solution' is specified by listing sequences of inputs and expected outputs as vectors. Maia treats the vectors as constraints, and creates the corresponding self-checking testbench, automating the processes of driving and testing timed device inputs and outputs, clock and reset generation, stability checking, pipeline handling, internal signal probing and forcing, time handling, and error reporting.

The Maia compiler, called mtv, is currently free and its base version is likely to remain free. It can be downloaded from this site. The compiler is available for 32 and 64-bit Linux, and 32-bit Windows.