Venktesh Shukla, President and CEO, Nusym Technology

The size and complexity of modern IC designs mandate extensive verification procedures to ensure that the design functionality is correctly implemented prior to fabrication. Constrained random simulation methodologies are simply not scaling due to their black box, open loop approach. Formal and semi-formal approaches leverage the design internals to improve effectiveness, but are impractical for large designs due to severe capacity limitations. As a result, design teams across the semiconductor industry are struggling to find ways to bring their exponentially increasing verification tasks back under control and to eliminate testing redundancies.

Adding to this verification challenge: At some point verification engineers are called upon to rule whether their designs have been sufficiently tested to be declared ‘functionally correct’…meaning that they have enough confidence that there are no bugs lurking in the code structure to move toward final implementation in silicon. As such, engineers are continuously working toward increasing verification confidence and tracking hard to reach areas of design.

In many ways the industry is called upon to try to capture the best aspects of the era two decades ago when the IC designers - who understood the design’s structure and intent - manually tested their own code. As such, “Intelligent Verification” approaches are emerging, which use both the design and the existing testbenches to accelerate verification closure.

These Intelligent Verification approaches also direct users as to why certain coverage points are not being hit. . They avoid the inefficiencies of constrained random methods by automatically associating target coverage points with relevant input variables. . Intelligent verification also ensures that no simulation cycles are wasted in verifying items which have already been tested.

More and more, verification methodologies must also address the problem of functional coverage - to provide feedback by identifying why some coverage points are not hit and isolating the coverage points that are simply unreachable.

Increasing verification confidence by reducing the risks associated with hardware device creation will have a major positive impact on the economic state and innovation of the electronics industry. By utilizing design insight in a similar manner as a designer would, but also leveraging the automation necessary to handle today's enormous designs, intelligent verification can help development organizations achieve verification closure in a manner which utilizes only a small portion of the engineering time and resources required today.