Cadence Design Systems, Inc. announced that engineers at Hitachi, Ltd. successfully implemented a new system-level verification environment for Ethernet routing/switching products using the Cadence® Incisive® Palladium® transaction-based acceleration technology. The new environment, based on the Palladium emulation system and the Incisive Enterprise Simulator, increases performance by potentially 100 times over previous HDL simulation. The environment supports con strained-random test generation and offers greater control and visibility over the simulation, debugging and verification process.

Hitachi and Cadence engineers collaborated on the integration of Palladium transaction-based acceleration (TBA) technology into Hitachi's future LSI development flow. Hitachi's original environment was classic HDL simulation based, with signal-based communication among the testbench components, coverage-driven Hitachi-proprietary verification IP (VIP), and the design under test (DUT). To create the new environment, Hitachi engineers used a two-step process. First, they modified their VIP to add transaction-level interfaces. Then they adapted the bus-functional models in their VIP, and together with the DUT synthesized/mapped those into their Palladium emulation system. This resulted in a total performance increase of over 100 times. This new environment including TBA will allow the Hitachi engineers to run variable network traffic and validate their complex network components on the Palladium system. Besides Palladium TBA, Hitachi engineers also leveraged other Palladium feat ures for in-circuit emulation, such as Cadence SpeedBridge® Adapters for Ethernet and ARM Logic Tiles, to facilitate emulation of verification interfaces and accelerate performance
Hitachi, Ltd. established a complex and high-quality functional verification environment with a 10,000 times performance boost by using Cadence® high-level synthesis and functional verification technologies and methodologies. Hitachi engineers verified a complex subsystem, including a next-generation PCI express core, by deploying the Cadence C-to-Silicon Compiler to accelerate their testbench on the Palladium® III acceleration/emulation system. The Cadence technology enabled Hitachi to achieve a more exhaustive set of functional test cases.
"We had to deliver high-quality designs in a short time window and therefore urgently needed to develop a platform that performed at a minimum of 1,000 times faster to verify more complex and larger combinations of functional test cases," said Nobuo Tamba, Ph.D, general manager of the Design & Development Operation, Micro Device Division at Hitachi. "Working with Cadence to apply new technologies created a breakthrough for our methodology."
First, Hitachi engineers employed SystemC® and transaction-level modeling (TLM) to develop complex testbench functions such as auto-pattern generation and auto-response logic, and a scoreboard. Then they deployed Cadence high-level synthesis to generate the synthesizable testbench, accelerating overall verification on a Palladium III system with Cadence transaction-based acceleration. Utilizing high-level synthesis is critical to achieving more productive system realization, one of the main pillars of the EDA360 vision.
"The success of this massive verification effort is the result of having two great teams of engineers working together with our superior system-level technologies and methodologies," said Christopher Tice, corporate vice president and general manager at Cadence. "This experience is a great example of how Cadence and our customers work together to achieve efficient system realization."
C-to-Silicon Compiler is a next-generation high-level synthesis technology; it automatically generates synthesizable Verilog RTL from timed or untimed C/C++/SystemC. The Palladium series delivers high system throughput, verification automation, and advanced debug to perform plan- and metric-driven system-level hardware/software co-verification.