GateRocket, Inc.announced the availability of the newest version of its RocketVision debugging software, further enhancing the company’s approach to reducing design time for high-end programmable devices from Altera and Xilinx.

RocketVision 5.0 introduces new capabilities that allow designers to select individual design blocks to run in their simulator or GateRocket's RocketDrive hardware verification system, the industry's only Device Native approach to debug and verification. The features enable engineers to find and fix bugs faster, and avoid unnecessary re-runs of time-consuming synthesis-to-place-and-route iterations, reducing overall design bring-up time.

The new enhancements improve the overall efficiency of RocketVision, a software-based debugging tool that is used in conjunction with third party simulation tools and GateRocket's RocketDrive hardware verification product. It provides simulators with visibility into the FPGA hardware and enables automated diagnosis by comparing intended behavior with actual results in the FPGA. With the new software release, designers now have the ability to move instances of one or more design blocks that were
executing in the FPGA to run in the simulator.

The user can then make changes to the RTL to fix bugs in their design and simulate them in software while the rest of the design executes in the native FPGA hardware in the RocketDrive.

New features streamline debug process

The new SoftPatch feature allows engineers to try a "soft" RTL fix to the FPGA without rerunning synthesis and place-and-route, eliminating hours of unproductive waiting time. Typically, when a bug is discovered, each correction requires a new synthesis and place-and-route cycle, and it can take days to resolve each bug. This is especially problematic in complex FPGA designs which commonly have large amounts of unfamiliar IP and hundreds of thousands of design elements. The SoftPatch feature provides an intuitive and efficient way to sequence through each bug and test fixes for them without re-building the FPGA. In this way the user can verify multiple fixes in a single day and then perform an overnight build that encompasses all the changes.

The new version of RocketVision also includes an enhanced AutoCompare features that helps identify bugs at the block or full-chip level. It allows designers to automatically compare the signals between the RTL and hardware representations of the complete FPGA design and highlights any differences that occur. This significantly simplifies the debugging process and helps quickly identify the location of each divergence.

Pricing and Availability

Both the latest versions of RocketDrive and RocketVision now support 64-bit versions of the industry's most popular simulators from Mentor, Cadence and Synopsys. This enables the use of the RocketDrive with 64-bit simulation servers, which are increasingly necessary to handle the largest complexity FPGA designs. RocketVision 5.0 is a RocketDrive option and is available immediately with a starting price of $9,500.