Forte Design Systems today launched Cynthesizer Ultra, its high-level SystemC synthesis software tightly integrated with its CellMath product family to create better designs faster. Additionally, Forte’s flagship Cynthesizer SystemC high-level synthesis software includes new capabilities that reduce design time, improve power utilization and accelerate verification performance. Both products, available now in volume shipments, simplify hardware and electronic system level (ESL) design to improve circuit performance and reduce chip costs.

Introducing Cynthesizer Ultra
Forte’s CellMath technology and patented intellectual property (IP) offers improved quality of results by creating better datapath components. Integrating Cynthesizer with CellMath Designer™ datapath optimization and CellMath intellectual property (IP) gives design teams a way to create better designs using more optimized building blocks faster.

Cynthesizer Ultra uses CellMath Designer as an embedded datapath optimization capability to create datapath components as needed for use in the high-level synthesis process. These products work together to perform automated design-space exploration that will search for the best set of components for each individual design. With these techniques, Cynthesizer Ultra improves power consumption and timing, and reduces area by up to 40% compared to previous versions.

Cynthesizer Ultra adds access to the CellMath IP library including advanced, floating point functional units used by leading-edge graphics companies. This IP can be accessed directly from SystemC through an automated flow.

Features for Improved Design, Verification, Quality of Results
Cynthesizer includes a new schedule analysis detail view. This allows designers to converge on their final design more quickly by giving them specific direction to correct or improve areas of the design that may not meet their quality of results (QoR) goals. High-level synthesis automatically builds the design “schedule” that includes creation of the datapath and finite state machine (FSM) to meet a given set of user-directed and/or hardware design constraints. When these constraints cannot be met, Cynthesizer gives the user specific direction for further input, reducing the design time needed.

Cycle Accurate simulation technology improves verification performance. Using Cynthesizer’s automated methodology management software, designers can quickly execute behavioral simulations, high-level synthesis and utilize Cynthesizer Cycle Accurate simulation to accelerate the output RTL implementations. With speeds up to 20x over traditional register transfer level (RTL) simulation, designers have a high-performance, cost-effective and integrated solution to meet their verification challenges.

Cynthesizer also includes updates to its CynWare IP interface library. Designers can use its extensive pre-verified library and new faster memory interface support for greater flexibility, better performance and lower power.

Additional features and optimizations further reduce circuit power utilization and improve tool runtime and capacity.

Forte will demonstrate Cynthesizer, Cynthesizer Ultra, and its CellMath family of products in Booth #750 at the 47th Design Automation Conference (DAC) June 14-16 at the Anaheim Convention Center in Anaheim, Calif. To schedule a private demonstration of Cynthesizer, contact: sales@ForteDS.com.

Availability and Pricing
Cynthesizer and Cynthesizer Ultra are shipping now. Cynthesizer comes standard with Forte’s transaction level modeling (TLM) synthesis capability, complete memory generation subsystem, fixed-point support and streaming interface IP. Cynthesizer Ultra adds the CellMath datapath optimizer and floating-point support. U.S. pricing starts at $275,000. Cynthesizer’s Partitioning and Interface Generator features start at $40,000 (U.S.) as an add-on to Cynthesizer.