Dr. Ralph Marlett and Kiran Vittal of Atrenta have written a paper proposing a solution to a common DFT problem. The paper is available by visiting this site. Once there select the paper from the list by clicking on the title.

There has been an enormous push for design-for-test (DFT) at the register transfer level for the past several years. RTL designers are now faced with requirements to comply with strict DFT guidelines to meet ever-tighter design schedules even though the designer may not understand all the complexities of defect models and testability techniques. SpyGlass DFT provides the platform and ease of use to RTL designers to quickly identify and fix testability issues without having to become a test expert.

Production testing for complex chips usually involves multiple test methods. Scan based automatic test pattern generation (ATPG) for stuck-at defect model has been the standard for many years, but experience as well as a number of theoretical analyses have shown that the stuck-at fault model is incomplete. Many devices pass very high coverage stuck-at tests and still fail to operate in system mode.

The test clocks in traditional stuck-at testing are designed to run on test equipment at frequencies lower than the system speed. At-speed testing requires test clocks to be generated at the system speed and these clocks are often shared with functional clocks from a phase locked loop (PLL) clock source. Any additional test clocking circuitry affects functional clock skew and thus the timing closure of the design. SpyGlass DFT DSM is designed to specifically address the problems associated with timing closure due to at-speed DFT.

This white paper demonstrates a solution for facilitating at-speed test at the register-transfer level. The RTL approach is important, because designers and test engineers usually verify the test coverage only at the gate level during the final ATPG stage. This RTL solution thus saves weeks of effort by fixing potential issues up front.

The SpyGlass DFT DSM solution is the industry’s first tool which will accelerate design turnaround times by identifying timing closure issues caused by at-speed testing – early at RTL. It provides accurate RTL fault coverage estimation for transition delay testing, together with diagnostics for low fault coverage, early in the design flow, to achieve high test quality with minimum design iterations.