Exploiting Concurrency, the Next Frontier

David Kung, Chair, Design Automation Technical Committee, IEEE Council on EDA

The technology disruption that will have the most pervasive impact on EDA is the plateauing of single-thread performance and the emergence of the "many-core" as the proxy for performance doubling. Historically, design tools have been relying on the doubling of single-thread performance every two years or so to keep up with the unrelenting increase of design complexity. In the future, design tools must leverage multi-processing and multi-threading to meet that challenge.

This is quite a tall order since the majority of the tool codes are developed as sequential programs. Concurrency requires mutual exclusion and locking mechanisms to avoid deadlocks and unpredictable outcomes so that the software will function correctly. To achieve the desired speed up, the overhead of maintaining multiple threads and processes must be minimized to circumvent the barrier imposed by Amdahl's Law. Scalability will become one of the first order criteria for a good algorithm. A parallel software development environment will become a necessity to provide profiling and debugging instead of just a productivity aid.

EDA vendors and industrial design automation groups are already addressing this parallelization issue, perhaps in a piece-meal manner initially. The effort will redouble in the course of the next several years to holistically implement parallelism across the whole tool flow. An enormous challenge is the transition of the legacy codes into the new parallel paradigm. Patching up existing programs by adding multi-processing and multi-threading is a huge endeavor in and of itself and is extremely error prone. Instead of putting new wine in old wineskin, I argue that the investment is better served by starting from scratch and building from the ground up. Therefore, startups have this rare opportunity to gain a competitive edge over the incumbents, who have to contend with years or even decades of legacy.

As the parallel initiative progresses, we will find that the current parallel software development environment is inadequate for complex EDA applications. EDA tools are highly computational and memory intensive, and could have extremely long runtimes. Existing profiling and tuning tools might be adequate for less technical applications but could add significant overheads when applied to EDA applications. As a result, EDA vendors could lead the way in augmenting existing parallel software environment and leverage it as an entry into adjacent and potentially lucrative spaces. All these disruptions do have a silver lining -- given the right scalable algorithms, these "many-core" machines can speed up design tools by quantum leaps over what can be attained by increasing single-thread performance alone.

I predict that we are at the dawn of unprecedented design productivity, precipitated by parallelization of EDA tools. Both the IEEE Design Automation Technical Committee (DATC) and the Computer-Aided Network DEsign (CANDE), under the auspices of the Council on EDA (CEDA), are spawning new initiatives to help make this a reality.

Comments

We would Agree--A New Architecture Is Needed

In the area of place and route, a new architecture is needed to allow optimium parallelization not just of the "easy to parallelize" parts like floorplanning and routing, but the core features like the timing analyzer and associated extraction, signal integrity and other engines. It also requires extremely fine grain decomposition of the computing tasks. Mentor Graphics has a whitepaper available that explains many of the issues involved: http://www.mentor.com/products/ic_nanometer_design/techpubs/accelerate-d...

Concurrency in EDA

Hi David,

I am interested in this area and have worked on parallelizing EDA applications as a consultant and now at Cadence.
http://software.intel.com/en-us/blogs/2009/08/31/why-parallel-processing... and the followon blogs are a discussion I have been trying to start.

If you are starting any industry wide efforts I would be happy to participate if it makes sense.

Tom Spyrou
Cadence Distinguished Enginerr
Parallel Processing
Hierarchical Implementation