This has been a particularly busy week in EDA. What follows are the summations of the most important stories not covered by GABEonEDA in details.

Atrenta - Atrenta Inc.announced that it has joined the Cadence System Realization Alliance. The initial focus for the alliance will be to verify that output of the Cadence C-to-Silicon Compiler passes a set of high-level synthesis SpyGlass rules that will be jointly developed by Cadence and Atrenta.

Synopsys - Synopsys introduced New DesignWare ARC EM Processor Family for Embedded Applications. The DesignWare ARC EM4 and ARC EM6 are the first processor cores built with the new ARCv2 instruction set architecture (ISA) and pipeline, delivering up to 25 percent more performance than existing ARC cores, while significantly reducing size and power by up to 15 percent. The ARCv2 ISA is implemented with a new scalable, low-latency pipeline that enables the development of advanced processor cores with the optimum balance of performance, power consumption and size for a broad range of cost- and power-sensitive embedded applications.

Cadence - Cadence reported third quarter 2011 revenue of $292 million, compared to revenue of $238 million reported for the same period in 2010. On a GAAP basis, Cadence recognized net income of $28 million, or $0.10 per share on a diluted basis in the third quarter of 2011, compared to net income of $127 million, or $0.48 per share on a diluted basis in the same period in 2010. GAAP net income for the third quarter of 2010 included $148 million in income tax benefit related to the settlement of an Internal Revenue Service examination of Cadence's federal income tax returns for the tax years 2000 through 2002.
Using Cadence's non-GAAP measure, net income in the third quarter of 2011 was $37 millions, or $0.14 per share on a diluted basis, as compared to net income of $11 million, or $0.04 per share on a diluted basis in the same period in 2010.

Imperas - Imperas, a member of the ARM Connected Community, has released its models of the Cortex-A9 MP Core and Cortex-A5 UP ARM processor cores, including the 1, 2, 3 and 4-core versions of the Cortex-A9 MPCore. Models of the Cortex-A9 MPCore and Cortex-A5 UP are now available from Open Virtual Platforms (OVP), including example virtual platforms incorporating the cores and support for the cores in Imperas' advanced software development tools.

Imperas also announced the interoperability of its OVP Fast Processor Models and advanced software Multiprocessor/Multicore Verification, Analysis and Profiling (M*VAP) tools with the Cadence Virtual System Platform. Imperas also detailed the development of the OVP Fast Processor Model of the Xilinx MicroBlaze soft processor core. This model of the Xilinx MicroBlaze will be available with certain versions of the Zynq-7000 EPP Virtual Platform as an extension to the virtual platform.

CEVA - CEVA, Inc. announced its financial results for the third quarter ended September 30, 2011. Total revenue for the third quarter of 2011 was $14.8 million, an increase of 39% compared to $10.7 million reported for the third quarter of 2010. Third quarter 2011 licensing revenue was $5.2 million, representing an increase of 17% when compared to $4.5 million reported for the same quarter a year ago. Royalty revenue for the third quarter 2011 was $8.8 million, an increase of 67% compared to $5.2 million reported for the third quarter of 2010. Revenue from services for the third quarter of 2011 was $0.9 million, a decrease of 12% compared to $1 million reported for the third quarter of 2010.

Dassault Systèmes - The Company announced the acquisition of Elsys, a provider of interactive electrical engineering and disruptive multi-discipline generative schematics solutions. Elsys generative technology enables the automatic creation of millions of 2D schematics from functional-logical master data, thereby eliminating the tedious, costly, and error-prone process of interactive manual creation of schematics. The goal of the Elsys acquisition is to provide a unique solution allowing Dassault Systèmes customers to associate schematic documents to the real product’s behavior. In addition, all associated schematics related to the design, manufacturing and services of electrical systems will be generated automatically from the functional-logical description. Eventually, thanks to the unique V6 convergence platform, Dassault Systèmes will be able to provide revolutionary multi-disciplinary integrated solutions, from electrical to fluidics to electronics.