John Sanguinetti, Chief Technology Officer, Forte Design Systems

In 2010 we will see more technical activity than 2009, both in the creation and adoption of products that embody new technology.
High-level design will continue to grow in adoption as the available tools become more widely accepted. There will be more published examples of designs done with high-level synthesis, and they will be more complex. Front-end tools, such as integrated development environments (IDEs), debugging aids and high-level coverage tools, will come to market, making the whole high-level design ecosystem richer. This will mostly happen based on SystemC. Further, TLM 2 will gain increasing usage.

High-level IP will become more widely available. At DAC 2009, a common question was, “where’s the third-party, high-level IP?” In 2010, that question will have an answer because there will be vendors supplying a variety of IP with TLM models and associated RTL code.

Recently, there have been a number of new entrants in the field of high-level synthesis, promoting the perception that all high-level synthesis tools are roughly the same. Many of these tools can put out RTL code, but have no infrastructure and support for a real RTL flows. In short, they haven’t gone to market. There will be a shakeout in the coming year.

In 2010, high-level synthesis tools will be partitioned two ways: input language and product maturity. Those that use SystemC as an input language will be used for designs which have multiple blocks and non-trivial interfaces. Those HLS tools that take plain old C or C++ as input will be used for simpler designs which have a small number of blocks and simple interfaces. HLS tools will also be partitioned by product maturity: those that have significant customer usage and those that have not. In 2010, the high-level synthesis tools which use SystemC as input and have matured by extensive customer use will emerge. The others will become FPGA-only tools for prototyping or they will simply go away and be forgotten.

2010 will see new technologies to improve verification. There will be products to create coverage points, and products to help identify holes in test coverage. There will also be products to guide test creation in order to reach untested coverage points. Assertion-based verification will gain popularity. New simulation technologies, both hardware and software, will appear that will make incremental, but important, improvements to simulation throughput.

Further, new startups will appear. In fact, there is more startup activity now in EDA than there has been for the past several years. 2010 should be a year of overall improvement in the EDA industry.