Jasper Design Automation announced it is working with France’s EASii IC, a well-known European electronic-design consulting company, to accelerate the adoption of formal verification methods and increase understanding of how they apply across the entire spectrum of chip design, from architecture to signoff, with its customers.

EASii IC becomes the newest member of JasperLinks which creates comprehensive solutions integrating Jasper formal verification with other EDA solutions and services in the SoC flow. JasperLinks is open to companies in the design ecosystem including IP vendors, design services firms and consultants, and EDA partners.