Frank Schirrmeister, Director, Product Marketing, System-level Solutions, Synopsys, Inc.

For years, the EDA industry has waited for Electronic System-Level (ESL) design to find broader adoption. Probably the most significant change needed for this transition to occur is a move to higher levels of abstraction, at some level above the current entry-level referred to as Register Transfer Level (RTL). In previous transitions of this kind – for example when the majority of design entry shifted from the gate-level to RTL– the transition was manageable because the user base did not change. Hardware developers at the gate-level “grew up” to become hardware developers at the RT-level. Resistance was futile and Darwin took care of the rest, so to speak. The transition ahead of us is significantly more complicated, mostly because the user base must be extended beyond pure hardware developers.

Technology has never been the main obstacle to the broader adoption of ESL approaches. Yes, there are some shortcomings. High-level synthesis approaches are largely application-domain specific. A universal language above RTL for either verification or implementation has not been found yet, or if it is has been found, it has not been universally accepted. Even the term transaction-level modeling (TLM) was only recently sorted into generally acceptable buckets when the SystemC TLM-2.0 API was ratified at DAC 2008.

Until now, the two main issues preventing ESL adoption were the lack of pressure to overhaul existing development approaches and the lack of clear definition of a user base of developers who could actually adopt them.

First, the lack of pressure means that development teams were able “to get by” with existing approaches. Not enough projects failed by hitting a brick wall or so exceeded budget that they were terminated. All indications show that in 2010 we will finally reach the point at which traditional techniques will become insufficient to finish chip development projects on time and within budget. The driver here is not hardware, but the software, which not only has become dominant with respect to the overall development effort spent on projects, but also dictates when chips can go into volume production as they can no longer be sold without the software being ready.

Second, when moving beyond RTL, it was not quite clear which users would adopt the suggested design approaches. Were they algorithm designers automatically creating implementations based on the algorithm descriptions? Were they software developers defining the functionality of a design on virtual platforms and determining hardware implementation? Or were they hardware developers “growing up” to the next level? In the past niche applications were addressing only specific users. Going forward, verification is going to change that.

In 2010, verification will become the unifying driver enabling the transition to system-level to become a reality. While high-level synthesis was originally intended to reach implementation faster, its real impact is now measured by how it improves verification efficiency through performing more verification with earlier, faster but less accurate models. Verification of the hardware itself is also in transition; in the era of multiple embedded processors, it is now the software that becomes the test bench for the hardware of the chip. Not only is verification becoming more efficient that way, but it also can be re-used from virtual platforms through RTL, FPGA prototypes and the actual silicon.

With verification growing up and becoming smarter in 2010 and forward, ESL methodologies and ESL users will be unified with a common goal: verification of the overall system. Algorithm, software and hardware developers will also make sure verification re-use is possible. We have an exciting year ahead of us.